Semiconductor chip with fuse unit

Details Semiconductor chip with fuse unit Semiconductor chip with fuse unit

2002-06-25

2004-11-16

Nguyen, Van Thu (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S208000, C257S529000, C257S665000, C257S730000

Reexamination Certificate

active

06818957

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-193014 filed on Jun. 26, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, which has memory and a logic circuit unit mounted upon the same substrate. In particular, it is related to a semiconductor chip and a semiconductor module, which respectively include a fuse unit used for defect cell recovery in memory.
2. Description of the Related Art
Conventionally, a redundant memory structure, which has an internal defect cell recovery circuit, is widely employed in semiconductor memory chips. When there is a defect cell in a memory device, this redundant memory structure replaces it by using a spare cell.
With a semiconductor chip including this type of redundant memory structure, there is a region having a plurality of fuse units (hereafter referred to as a ‘fuse unit group’) on a portion of the defective memory recovery circuit.
Typically, with a semiconductor chip testing process, once the existence of a defect cell is confirmed with a tester and the specific address of the defect cell is identified, the corresponding fuse of the fuse unit is melted and blown by using a laser to store the address of the defect cell in the fuse unit.
Upon reading out a memory cell, the stored defect cell address and an inputted address are compared; if they match, a redundant cell is selected, otherwise, if they do not match, the cell of the inputted address is selected.
FIG. 1
is a planar view showing a configuration of a conventional memory chip
100
. As shown in the same Figure, with the memory chip
100
, electrode pad rows
200
for bonding are respectively arranged along ones of the edges of the chip. Inside thereof, a plurality of memory arrays
300
are arranged, and next to each memory array
300
a corresponding decoder circuit
500
and fuse unit group
400
are arranged.
Meanwhile, in recent years, due to reductions in mounting area and improvements in data transfer speed, memory embedded chips having memory and a logic circuit on the same substrate have come to be widely used.
FIG. 2
is a planar view showing a structural example of a conventional memory embedded chip
110
. As shown in the same figure, electrode pad rows
210
for bonding are arranged along all four edges of the chip, and a logic circuit unit
700
and a memory macro unit
610
are formed there inside.
The memory macro unit
610
includes memory
600
, which includes memory arrays and a decoder circuit, etc., and a fuse unit group
410
. The memory macro unit
610
includes a redundant cell configuration for defect cell recovery as with the case of the memory chip
100
. In this manner, the same memory functions as the conventional memory chip
100
may be included with merely the memory macro unit
610
, and normally, design of the memory macro unit
610
and design of the logic circuit unit
700
are independent of each other.
In recent years, calculation processing requested of the logic circuit has become more complex, and consequently, power consumption has increased. Together with such conditions, the number of power source terminals required for the chip has increased, and interconnects such as power source lines and signal lines for connecting the logic circuit unit within the chip to the electrode pads, which function as power source terminals, have also become more complex.
In addition, the memory capacity that is loaded upon the memory embedded chip together with the logic circuit unit has increased, and the space occupied by the memory macro unit relevant to the entire chip area has increased. As a result, it has become necessary for interconnects such as the signal lines and power source lines formed in the highest layer, which connect the logic circuit unit and the electrode pads, to pass over the top of the memory macro unit.
However, since the fuse melting/blowing operation is performed after forming the interconnects on the upper-most layer, these interconnects cannot be formed above the fuse unit group. Accordingly, as shown in
FIG. 2
, the interconnects
800
such as the power source lines and signal lines connecting, for example, the logic circuit unit
700
and the electrode pad
210
must be routed around the fuse unit group
410
. Therefore, the existence of the fuse unit group
410
places great constraints on the interconnect routing design for connecting each electrode pad
210
a
and the logic circuit unit
700
.
Meanwhile, with recent logic circuit unit LSI, the trend in increased integration continues, further increasing the number of input/output signal terminals on a chip. In addition, due to the increase in power consumption accompanying this, the number of power source terminals has been further increased. As a result, with the conventional mounting method where the electrode pads are connected to an external board via the wire bonding, the number of electrode pads is limited, causing situations to develop where the number of terminals may be insufficient. Therefore, recent semiconductor chips are utilizing mounting methods that make use of bumps.
FIG. 3
is a planar view showing a structural example of a memory embedded chip
120
using bumps. Electrode pad rows
210
are arranged along all four edges of the chip, and a logic circuit unit
700
and a memory macro unit
610
are formed there inside. Within the memory macro unit
610
, memory
600
and a fuse unit group
410
are formed.
On the chip surface, a plurality of bumps
900
, which are formed as, for example, protuberances of lead, are laid out in a two-dimensional pattern. Each electrode pad
210
b
is connected to each corresponding bump
900
by interconnects in the upper-most layer, and then via the bumps
900
is connected to an external board. More specifically, the input/output terminals are respectively connected to electrode pads
210
b
on the chip edge. These electrode pads
210
b
are further connected to bumps
900
, respectively, arranged on the chip surface. These bumps
900
are then connected to, for example, an external package board.
In this manner, in cases where bumps
900
are used, it is possible to increase the number of input/output terminals since the input/output terminals may be laid out on the chip surface in a two-dimensional pattern. In addition, since the distance between each bump terminal laid out in the two-dimensional pattern may be widened, connection with the external board also becomes easier.
Nonetheless, in this case as well, as shown in
FIG. 3
, the interconnect connecting each electrode pad
210
b
with a respective bump
900
must be routed around the fuse unit group
410
. This also causes there to be electrode pads that are not connected to a bump
900
, as shown in the same Figure.
In addition, bumps
900
may not be formed over the fuse unit group
410
. As a result, bumps cannot be laid out in an even pattern throughout the entire chip surface. In cases where the semiconductor chip is mounted on, for example, a package board, it is easy for stress to develop in the bumps due to differences in the thermal expansion of the chip and that of the package board. Accordingly, if the bumps are not laid out evenly throughout the chip surface, an imbalance in stress may develop making it easy for problems to occur such as the package peeling back.
Moreover, with an Application Specific Integrated Circuit (ASIC), since the memory macro unit upon the chip may be arranged at the discretion of each user, the location of the fuse unit group may also differ for each user depending on the arrangement of the memory macro unit. And since the arrangement of bumps may be affected by the position of the fuse unit, various changes may be possible depending on the user. Accordingly, assuming all of these combinations, it is extremely difficult to perform ASIC layout so that problems such as peeling back of the

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