Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2003-04-07
2004-06-01
Verbrugge, Kevin (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
06745287
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to control devices of disk array devices for storing data in a plurality of magnetic disk devices.
In view of the fact that the input/output (I/O) performance or throughput of a disk subsystem (referred to as a “subsystem” hereinafter) is less by approximately three to four orders of magnitude than the I/O throughput of main memories of computers which use semiconductor memory devices as their storage media, attempts have conventionally been made to reduce this difference, namely, to improve the I/O throughput of the subsystem. One prior known approach to improving the subsystem's I/O throughput is to use a system, called a “disk array”, for constituting the subsystem from a plurality of magnetic disk devices, such as fixed or “hard” disk drives (HDDs), which are applicable for use in storing data.
FIG. 2
shows an arrangement typical of one known type of disk array. This includes a plurality of channel interface (IF) units
411
for execution of data transmission between a mainframe
50
and a disk array controller
2
, a plurality of disk IF units
414
for execution of data transfer between HDDs
20
and the disk array control unit
2
, a cache memory unit
14
for temporarily storing data of the HDDs
20
, and a shared memory unit
15
for storing control information relevant to the disk array controller
2
(for example, information concerning data transfer control between the channel units
411
and disk IF units
414
and the cache memory unit
14
), wherein the cache memory unit
14
and shared memory unit
15
are arranged so that they are accessible from all of the channel IF units
411
and disk IF units
414
. With this disk array, the channel IF units
411
and disk IF units
414
are connected to the shared memory unit
15
on a one-to-one basis; similarly, the channel IF units
411
and disk IF units
414
are connected one by one to the cache memory unit
14
. This connection form is called a star connection.
The channel IF unit
411
has an interface for connection with the mainframe
50
and also a microprocessor (not shown) for controlling input/output with respect to the mainframe
50
. The disk IF unit
414
has an interface for connection to the HDDs
20
and a microprocessor (not shown) for controlling input/output relative to HDDs
20
. The disk IF unit
414
also executes RAID functions.
FIG. 3
shows the configuration of another known disk array. It includes a plurality of channel IF units
411
for execution of data transfer between a mainframe
50
and a disk array controller
3
, a plurality of disk IF units
414
for execution of data transfer between HDDs
20
and the disk array controller
3
, a cache memory unit
14
for temporarily storing data of the HDDs
20
, and a shared memory unit
15
for storing control information relevant to the disk array controller
3
(e.g. information concerning data transfer control between the channel units
411
and disk IF units
414
and the cache memory unit
14
), wherein each of the channel IF units
411
and disk IF units
414
is connected by a shared bus
130
to the shared memory unit
15
; whereas, each channel unit
411
and disk IF unit
414
is connected by a shared bus
131
to the cache memory unit
14
. Such a connection form is called a shared bus connection.
In order to make the architecture of a disk array scalable, the number of disk IF units must be increased according to the capacity of the disk (the number of logical volumes) connected to a disk controller. In addition, the number of channel IF units in the object disk array controller must be increased according to the necessary number of channels connected to the host computer. For a disk array controller that employs the shared bus connection form, however, increasing the number of channel IF units and disk IF units degrades the data transfer throughput of the access path between each of the channel IF units and/or the disk IF units and a cache memory unit or a shared memory unit which is to become scalable according to an increase in the number of channel IF units or disk IF units. This is because the shared bus becomes a bottleneck in making the access path throughput scalable.
Furthermore, in the case of the shared bus connection form, if a high performance microprocessor is employed for each of those channel IF units and/or the disk IF units, the transfer capacity of the shared bus cannot cope with the processor performance, thereby the shared bus can hardly keep up with the high speed operation of the processor.
Furthermore, in the case of the shared bus connection form, if an operation error occurs in any of those channel IF units (or disk IF units) connected to the shared bus, it is difficult to identify the error-detected channel IF unit (or disk IF unit).
On the contrary, in the disk array controller of the star connection form, it is possible to increase the internal path performance or throughput in a way proportional to the number of access paths being connected to either the shared memory unit or cache memory unit, which in turn makes it possible to increase the throughput of the internal paths in accordance with the add-in reconfiguration of the channel and disk IF units or alternatively with the performance of the processors being used. In addition, since the star connection is used between the channel IF and disk IF units and the cache memory unit or between the channel and disk IF units and the shared memory unit, it is easy to specify a channel IF unit (or disk IF unit) at which an operation failure has occurred.
In the disk array controller of the star connection form, increasing the number of those channel IF units or disk IF units which are built therein would result in an increase in the number of access paths between the channel and disk IF units and the cache memory unit and between the channel and disk IF units and the shared memory unit. Additionally, the throughput called for by disk array control devices tends to further increase due to employment of high-speed channels, such as a fiber optic channel, for connection between host computers and disk array controllers; therefore, in order to satisfy this need for improvement of the throughput, it should be effective to increase the number of access paths between the channel and the disk IF units and the cache memory unit and between the former and the shared memory unit to thereby improve the internal path throughput.
However, the amount of data in a single data segment or datum to be stored in the cache memory is much greater than the amount of data in a single control information item being stored in the shared memory. As an example, in a disk control device connected to a mainframe, a single datum being stored in the cache memory is several kilobytes (KB) or more or less (for example, 2 KB), whereas one control information item stored in the shared memory is several bytes or therearound (e.g. 4 bytes). As another example, in disk control devices connected to host computers of open architectures, a single datum as stored in the cache memory is several tens of bytes (e.g. 64 bytes), whereas a single control information item stored in the shared memory is about several bytes (e.g. 4 bytes). Accordingly, the amount of data to be transferred between the channel and the disk IF units and the cache memory unit is extremely greater than the amount of data being transferred between the channel and disk IF units and the shared memory unit, which leads to a need for letting the data width of an access path between the channel and disk IF units and the cache memory unit be wider than the data width of an access path between the channel and disk IF units and the shared memory unit. For instance, the access path of the former is constituted from a 16-bit width bus, whereas the latter is constituted from a 4-bit width bus. For this reason, increasing the line number of access paths between the channel and disk IF units and the cache memory unit would result in creation of a problem of shortage of the number o
Fujibayashi Akira
Fujimoto Kazuhisa
Tanaka Atsushi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Verbrugge Kevin
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