Method and apparatus for determining actual write latency...

Details Method and apparatus for determining actual write latency... Method and apparatus for determining actual write latency...

2001-06-06

2004-02-24

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S104000, C711S105000, C365S233100, C365S233500

Reexamination Certificate

active

06697926

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to high speed synchronous memory systems, and more particularly, to a method and apparatus for determining actual write latencies of memory devices and accurately aligning the start of data capture with the arrival of data at a memory device.
2. Description of the Related Art
In a typical computer system, a processor interfaces with a memory device over a bus, typically through a memory controller. When a controller submits a READ request to a memory device, the response from the memory device can be read by the controller from the bus after a delay of time, referred to as a READ “latency.” If a controller submits a WRITE request, a memory device in the memory system can then receive the data from the bus and start to capture the data for storage after a certain write “latency.”
The amount of latency can vary depending on the type of device. The amount of latency can also vary depending upon the type of request. For example, a memory device may require 10-15 nanoseconds to respond to a read request, but only 5-10 nanoseconds to respond to a write request.
A memory controller, in advance of issuing a memory request, typically stores a specified latency value for each type of request and for each type of device. Therefore, when issuing a request, the controller can determine the period of time that it must wait before providing data to or receiving data from the bus.
An exemplary computer system is illustrated in FIG.
1
. The computer system includes a processor
50
, a memory subsystem
10
, and an expansion bus controller
52
. The memory subsystem
10
and the expansion bus controller
52
are coupled to the processor
50
via a local bus
54
. The expansion bus controller
52
is also coupled to at least one expansion bus
56
, to which various peripheral devices
57
-
59
such as mass storage devices, keyboard, mouse, graphic adapters, and multimedia adapters may be attached.
The memory subsystem
10
includes a memory controller
40
which is coupled to a plurality of memory modules
30
-
32
via a plurality of signal lines
41
a
-
41
d
,
42
,
43
,
44
,
45
a
-
45
d
,
46
a
-
46
d
. The plurality of data signal lines
41
a
-
41
d
are used by the memory controller
40
and the memory modules
30
,
32
to exchange DATA. Addresses ADDR are signaled over a plurality of address signal lines
43
, while commands CMD are signaled over a plurality of command signal lines
42
. The memory modules
30
,
32
include a plurality of memory devices
11
-
14
and
15
-
18
, respectively, and respective registers
21
,
22
. Each memory device
11
-
18
is a high speed synchronous memory device. Although only two memory modules
30
,
32
and associated signal lines
41
a
-
41
d
,
42
,
43
,
44
,
45
a
-
45
d
,
46
a
-
46
d
are shown in
FIG. 1
, it should be noted that any number of memory modules can be used. In addition, although only four memory devices are shown per memory module, fewer or more memory devices can be provided on each module.
The plurality of signal lines
41
a
-
41
d
,
42
,
43
,
44
,
45
a
-
45
d
,
46
a
-
46
d
which couple the memory modules
30
,
32
to the memory controller
40
are known as the memory bus
15
. The memory bus
15
may have additional signal lines which are well known in the art, for example chip select lines, which are not illustrated for simplicity. Each column of memory devices
11
-
14
,
15
-
18
which span the memory bus
15
is known as a rank of memory. Generally, single side memory modules, e.g. SIMMs (Single Sided In-Line Memory Modules) such as the ones illustrated in
FIG. 1
, contain a single rank of memory. However, double sided memory modules, e.g. DIMMs (Dual In-Line Memory Modules) containing two ranks of memory may also be employed.
A plurality of data signal lines
41
a
-
41
d
couple the memory devices
11
-
18
to the memory controller
40
. Read data is output serially synchronized to a read clock signal RCLK, which is driven across a plurality of read clock signal lines
45
a
-
45
d
. The read clock signal RCLK is generated by a read clock generator
41
which is applied to the memory devices
11
-
18
of the memory modules
32
,
30
, and to the memory controller
40
.
Although shown as separate from the memory modules
30
,
32
for illustrative purposes, the read clock generator
41
is often provided within the memory devices
11
-
18
themselves and the read clock signals may be derived from other clock signals applied to the memory devices.
Write data is input serially synchronized to the write clock signal WCLK, which is driven across a plurality of write clock signal lines
46
a
-
46
d
by the memory controller
40
. Commands and addresses are clocked using a command clock signal CCLK which is driven by the memory controller across the registers
21
,
22
of the memory modules
30
,
32
, to a terminator
48
. The command, address, and command clock signal lines
42
-
44
are directly coupled to the registers
21
,
22
of the memory modules
30
,
32
. The registers
21
,
22
buffer these signals before they are distributed to the memory devices
11
-
18
of the memory modules
30
,
32
. The memory subsystem
10
therefore operates under a three clock domain, i.e., a read clock domain governed by the read clock RCLK, a write clock domain governed by the write clock WCLK, and a command clock domain governed by the command clock CCLK. In a two clock domain, the third clock domain CCLK does not exist and the write clock WCLK serves the dual purpose of write data capture and command/address capture.
When a memory device
11
-
18
accepts a read command, a data associated with that read command is not output on the memory bus
15
until a certain amount of time has elapsed as determined by the command clock CCLK. This time is known as device read latency CL. A memory device
11
-
18
can often be programmed to operate at any one of a plurality of device read latencies, ranging from a minimum device read latency (which varies from device to device) to a maximum read latency.
Thus, the read latency CL of each device is measured relative to the command clock (CCLK) in a three clock domain as described above, or the write clock WCLK in a two clock domain as described above, since in the two clock domain the write clock WCLK serves the dual purpose of write data capture and command/address capture. Current specifications for a two clock domain require a write latency of CL-
1
, i.e., one clock cycle less than the read latency, or CL-
2
, i.e., two clock cycles less than the read latency. However, because the read clock signal RCLK is typically compensated for by a delay locked-loop circuit with an output model of the system, the true read latency CL relative to the write clock WCLK is unknown. Therefore, specifying the write latency relative to the read latency may not accurately predict the arrival of data at the device relative to the write clock.
In addition, the write latency of each device is only one portion of the write latency seen by the memory controller
40
. This total latency seen by the memory controller, known as system latency, is the sum of the device write latency and the latency caused by the effect of signal propagation time between the memory devices
11
-
18
and the memory controller
40
. If the signal propagation between each memory device
11
-
18
and the memory controller
40
were identical, the latency induced by the signal propagation time would be constant and equally affect each memory device
11
-
18
. However, as
FIG. 1
illustrates, commands CMD, addresses ADDR, and the command clock CCLK are initially routed to registers
21
,
22
before they are distributed to the memory devices
11
-
18
. Each memory device
11
-
14
,
15
-
18
on a memory module
30
,
32
is located at a different distance from the register
21
,
22
. Thus each memory device
11
-
14
will receive a command and/or data issued by the memory controller
40
at different times. Additionally, there are also dif

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