Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2002-06-18
2004-11-09
Duda, Kathleen (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S394000, C430S396000
Reexamination Certificate
active
06815148
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and more particularly, to such a method of manufacturing a semiconductor device as having a step of etching an underlying layer by using a photo resist film as a mask. The present invention further relates to a method of forming a photo-mask having a pattern such as a hole which is to be transferred to a photo resist film that is used as a mask for etching an underlying layer. The present application is based on Japanese Patent Application No. 2001-185976, which is incorporated herein by reference.
2. Description of the Related Art
In the lithography step, which is one of the steps of a process for manufacturing semiconductor devices, a resist film is applied to an underlying layer formed on a semiconductor substrate, and the exposure and development are performed on the resist film by use of a photo-mask to form a resist pattern (in other words, the pattern of the photo-mask being transferred to the resist layer), followed by the etching or impurity introduction being performed on the underlying layer by use of the resist pattern as a mask.
More detailed description will be made on the so-called dual-damascene interconnection structure of a trench first process type, which is taken as an example, with reference to
FIGS. 5A
to
5
D. The dual-damascene interconnect having a trench interconnect (wiring) formed in a trench of an interlayer dielectric layer and a via hole electrically connecting the trench interconnect to a conductive layer (or an impurity region) formed under the interlayer dielectric layer. As shown in
FIG. 5A
, an interlayer dielectric
103
is formed with a prescribed film thickness on a semiconductor substrate
101
in which a conductive layer
102
of the underlying layer is formed. Next, as shown in
FIG. 5B
, a first resist film
104
is applied and by performing the exposure and development of the first resist film
104
by use of a first photo mask
105
having a mask pattern corresponding to an interconnect trench, a first resist pattern
106
of pattern shape corresponding to a trench inter connect is formed. After that, the above-described interlayer dielectric
103
is selectively etched to a prescribed thickness by use of this first resist pattern
106
as a mask and an interconnect trench
107
is formed. Subsequently, as shown in
FIG. 5C
, a second resist film
108
is applied to the whole surface and by performing the exposure and development of the second resist film
108
by use of a second photo mask
109
having a via pattern, a second resist pattern
110
of pattern shape corresponding to a via is formed in the above-described interconnect trench
107
. After that, by use of this second resist pattern
110
as a mask the above-described interlayer dielectric
103
is selectively etched until the conductive layer
102
of the underlying layer is reached, whereby a via hole
111
that opens the conductive layer
102
of the underlying layer is formed. In addition, as shown in
FIG. 5D
, by filling the above-described interconnect trench
107
and via hole
111
with a conductive material
112
, a trench interconnect
113
is formed in the interconnect trench
107
and a via
114
that electrically connects the trench interconnect
113
and the conductive layer
102
of the underlying layer is formed in the via hole
111
.
In such process as described above, since the second resist film
108
is coated after forming the interconnect trench
107
, the second resist film
108
is not formed with a uniform thickness, but formed such that its thickness over the inner (or central) portion of the interconnect trench
107
is smaller than that over the outer (or edge) portion of the trench
107
. The inventor of the present invention has revealed that the difference in thickness of the photo resist film
18
over the trench
107
causes problems as described below.
Specifically, a via hole is not always formed in substantially the middle of an interconnect trench, and it is formed at a various kind of positions based on where airing layer or an impurity region to which the via hole should be connected is formed. For example, as shown in
FIG. 6A
, a via hole
111
A is opened in a position near the center in the width direction of a trench interconnect
113
and a via hole
111
B is opened in a position near an edge, as shown in FIG.
6
B. As described above, the second resist film
108
is not formed with the uniform thickness into the trench interconnect
113
, but the second resist film
108
is formed with a film thickness in the region of both edge sides of an interconnect trench
107
being larger than that in the region of the middle of the interconnect trench
107
, as shown in FIG.
6
B. For this reason, if a pattern of the photo mask
109
having a via hole pattern
111
A and
111
B is transferred to the second resist film
108
to made a second resist pattern
110
for forming a via hole is formed, the resist pattern
110
is formed to have a pattern opening
110
A having substantially the same size as a via hole pattern
111
A. However, on the other hand, the resist pattern
110
is formed to have a pattern opening
110
B having a tapered shape in the depth direction of the opening in the region on both sides of the interconnect trench
107
because the exposure at the bottom of the second resist film
108
decreases due to the resist film thickness being large in the region on both sides of the interconnect trench
107
. With the result that although the size of the pattern opening
110
B on the surface of the second resist film
108
is formed to have substantially the same size as the via hole pattern
111
B, the size of the pattern opening
110
B at the boundary between the second resist film
108
and an interlayer dielectric
103
, i.e., on the bottom surface of the second resist film
108
, becomes smaller than the via hole pattern
111
B. Therefore, if a via hole is opened by etching the interlayer dielectric
103
by use of such a resist pattern as a mask, the diameter size of a via hole
121
A formed in the middle region becomes almost as designed, however, the diameter size of a vie hole
121
B formed in the edge region on both sides becomes smaller than a design size, thus a via resistance of the via hole
121
B is larger than it is designed.
As described above, a size of a via hole transformed in substance from a photo mask to a photo resist film varies due to a lack of uniformity of a film thickness of the photo resist film, which is caused by a surface shapes i.e. a surface concavity and convexity (uneven surface) of an underlayer film due to steps of an underlying layer.
It should be noted that a size of a pattern that is actually transferred to a photo resist film is discussed in Japanese Patent Laid-Open No.2000-292903 (hereinafter, a referential document 1) and Japanese Patent Laid-Open No. 2001-85583 (hereinafter, a referential document 2). In the referential document 1, it is pointed out that the size of a pattern actually transferred to the photo resist film is affected by the difference in thickness of the photo resist film. However, the document 1 does not address at all about how and where the difference in thickness of the resist film is generated. Especially, it does not recognize that a surface concavity and convexity of an underlayer which is to be selectively etched by use of a photo resist film, causes variation in film thickness of that photo resist film. Rather, in accordance with the teachings of the referential document 1, a variation of the actually-transferred size of the pattern caused by the film thickness of a photo resist film is solved by providing an anti-reflection layer on and/or under the photo resist layer. In addition, the document 1 suggests that a variation of a size of a pattern that has been actually transferred on a photo resist film is caused by the layer structure of the underlayer film which is subjected to etching, rather than by the variation of
Duda Kathleen
Foley & Lardner LLP
NEC Electronics Corporation
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