Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-09
2004-08-17
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S295000, C257S296000, C257S306000, C257S307000, C257S308000, C257S309000
Reexamination Certificate
active
06777736
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2001-71791, filed in Mar. 14, 2001, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a capacitor and a method of manufacturing the same.
2. Description of the Prior Art
As one of the nonvolatile memory that can store the information after the power supply is turned off, there is known the FeRAM (Ferroelectric Random Access Memory) having the ferroelectric material. The FeRAM has the structure that can store the information by utilizing the hysteresis characteristic of the ferroelectric material, and permits the high speed operation, and has the low power consumption. Thus, the future development of the FeRAM is anticipated as the nonvolatile memory that permits the large number of times of the writing operation.
FIGS. 1A and 1B
show an example of a circuit diagram of an FeRAM memory cell respectively.
FIG. 1A
show an example of a circuit diagram of the type in which two transistors T
11
, T
12
and two capacitors C
11
, C
12
are employed to store one-bit information (referred to as a “2T2C type” hereinafter). The 2T2C type FeRAM memory cell executes an complementary operation to store “1” or “0” data into one capacitor and store the opposite data into the other capacitor. At the time of decision of the data, polarization states of both capacitors C
11
, C
12
are read, and then the data decision is carried out by using difference between them.
FIG. 1B
is a circuit diagram of the type in which one transistor T
o
and one capacitor C
o
are employed to store one-bit information (referred to as a “1T1C type” hereinafter). The 1T1C type employs one transistor and one capacitor for one-bit information. Also, the 1T1C type needs the reference capacitor C
1
that generates the reference voltage to decide that the charge read from the memory cell is the data of “1” or the data of “0”. The polarization of the reference capacitor C
1
is inverted every time when the data is read out. The decision of data is executed based on the large or small relationship between the potential of the capacitor C
o
of each memory cell and the potential of the reference capacitor C
1
. The reference capacitor C
1
is connected to an end portion of each bit line BIT. Ideally, it is desired that the potential of the reference capacitor C
1
should be set to an intermediate potential between the voltage V
1
at which “1” is written into the memory cell and the voltage V
0
at which “0” is written into the memory cell.
The 1T1C type memory cell can reduce a cell area to almost half rather than the 2T2C type FeRAM memory cell.
FIG. 2
shows a plan view of a structure in which the arrangement of the 2T2C type memory cell is applied to the 1T1C type memory cell.
In
FIG. 2
, a plurality of stripe-like capacitor lower electrodes
103
that extend in the Y direction are formed at an interval over a device isolation layer
102
on a semiconductor substrate
101
in the X direction. Then, ferroelectric films
104
each having the almost same shape as the capacitor lower electrode are formed on the capacitor lower electrodes
103
. Then, a plurality of capacitor upper electrodes
105
are formed on the ferroelectric films
104
to be aligned in the Y direction. One capacitor C
o
consists of the capacitor upper electrode
105
, the ferroelectric film
104
, and the capacitor lower electrode
103
.
Also, a pair of transistors T
o
are formed in active regions, that are surrounded by the device isolation layer
102
, on both sides of the capacitor upper electrode
105
on the semiconductor substrate
101
. Then, a plurality of capacitor upper electrodes
105
formed on the capacitor lower electrodes
103
are connected sequentially to the transistor T
o
on one side and the transistor T
o
on other side alternatively.
Two transistors T
o
are formed in one active region surrounded by the device isolation layer
102
. Two gate electrodes
106
that are also used as word lines WL extending in the Y direction are formed in the active region via a gate insulating film (not shown). Impurity diffusion areas
107
a
,
107
b
,
107
c
are formed in the active regions on both sides of two gate electrodes
106
.
Bit lines BIT connected to the impurity diffusion area
107
b
in the center of the active region are formed over the capacitor C
o
and the transistor T
o
so as to extend in the X direction. Also, the impurity diffusion areas
107
a
,
107
c
on both ends of the active region are connected to the capacitor upper electrode
105
via a local-interconnection wiring
108
that is formed below the bit line BIT along the bit line BIT.
In
FIG. 2
, an interlayer insulating film formed on the semiconductor substrate
101
is omitted.
In
FIG. 2
, since a plurality of transistors T
o
existing in the Y direction are connected to a plurality of capacitor upper electrodes
105
formed on the side of the transistor every other electrode respectively, a wide margin exists between the transistors T
o
.
Therefore, as shown in
FIG. 3
, in order to place the capacitor C
o
in the area between the transistors T
o
existing in the Y direction, it is set forth in Tatsuya Yamazaki et. al, “Advanced 0.5 &mgr;m FEAM Device Technology with Full Compatibility of Half-Micron CMOS Logic Device” 1997 IEEE IEDM to form the capacitor upper electrodes
105
in a zigzag fashion. Accordingly, an interval between the transistors T
o
in the X direction is narrowed.
FIG. 4A
is a sectional view of the memory cell shown in
FIG. 3
taken along a I—I line, and
FIG. 4B
is a sectional view of the reference capacitor connected to the bit line BIT.
In
FIG. 4A
, the device isolation layer
102
and the transistor T
o
on the semiconductor substrate
101
are covered with a first interlayer insulating film
111
and a second interlayer insulating film
112
. Holes are formed in the first interlayer insulating film
111
on the impurity diffusion areas
107
a
,
107
b
,
107
c
respectively, and contact plugs
109
a
,
109
b
,
109
c
are buried in these holes respectively. The capacitors C
o
are formed on the second interlayer insulating film
112
, and a third interlayer insulating film
113
is formed on the capacitors C
o
. Also, the local-interconnection wirings
108
are formed on the third interlayer insulating film
113
. The local-interconnection wirings
108
are connected to the capacitor upper electrode
105
via a hole in the third interlayer insulating film
113
respectively, and also connected to the contact plugs
109
a
,
109
c
on the end portions of the active regions via another holes in the second and third interlayer insulating films
112
,
113
respectively. Also, the bit line BIT is formed on a fourth interlayer insulating film
114
that covers the local-interconnection wirings
108
. The bit line BIT is connected to the contact plug
109
b
in the center of the active region via a hole that is formed in the first, second, third and fourth interlayer insulating films
111
,
112
,
113
,
114
.
In
FIG. 4B
, a reference capacitor C
1
consisting of a lower electrode
115
, a ferroelectric film
116
, and an upper electrode
117
is formed on the second interlayer insulating film
112
formed over the semiconductor substrate
101
. The reference capacitor C
1
is covered with the third interlayer insulating film
113
. Also, a local-interconnection wiring
118
that is connected to the upper electrode
117
of the reference capacitor C
1
via a hole is formed on the third interlayer insulating film
113
. This local-interconnection wiring
118
is extended to the outside to pass over the upper electrode
117
. Also, the bit line BIT connected to another reference capacitor is formed over the reference capacitor C
1
via the fourth interlayer insulating film
114
.
By the way, following problems ex
Miyazawa Hisashi
Saigoh Kaoru
Suzuki Hideaki
Yamazaki Hirokazu
Fujitsu Limited
Soward Ida M.
Zarabian Amir
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