Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-11
2004-06-15
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S412000, C257S413000, C257S751000
Reexamination Certificate
active
06750503
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a process for producing the same, and more particularly to a semiconductor device with an MIS type transistor and a process for producing the same.
To attain higher performance and higher integration of devices, semiconductor devices have been progressively scaled down over the years, necessitating incorporation of low-resistance materials into the electrode materials. It is thus desirable to incorporate a metal also into the MOS transistor gate electrode.
In case of high speed CMOS devices, on the other hand, low threshold voltage and low gate resistance alone are not enough to attain both higher performance and higher integration. It is also required to reduce the gate/contact pitch. Conventional technologies of satisfying these requirements include a SALICIDE technology of self-aligned silicidation of gate polycrystalline silicon and source/drain regions, a technology using POLICIDE structure, i.e. using a gate of polycrystalline silicon/silicide-stacked structure, a technology using a gate electrode of polycrystalline silicon/high melting point metal-stacked structure, etc.
However, the SALICIDE technology is difficult to use together with a self-aligned contact technology and thus is difficult to reduce the layout pitch. The POLICIDE structure is so high in the sheet resistance that it is difficult to obtain a sufficiently low gate resistance. This is a problem of the POLICIDE structure. Thus, the desirable gate electrode structure capable of satisfying the aforementioned requirements is a metal/polycrystalline silicon-stacked structure.
However, such a stacked structure has a low thermal stability and even if tungsten, i.e. high melting point metal, is used as the metal, reaction takes place between the metal and silicon during the heat treatment at about 650° C., resulting in an increase in resistance, degradation of layer surface state, dielectric breakdown, etc, which are examples of other problems arising. To solve these problems, a structure of inserting a metal nitride layer as a reaction barrier between the metal and the polycrystalline silicon (metal/reaction barrier/polycrystalline silicon-stacked structure) has been proposed (e.g. '98 IEDM Technical Digest, pp. 397-400).
Use of the tungsten nitride layer as a reaction barrier as mentioned above, still suffers from the following problems:
(1) Contact resistance between tungsten nitride and polycrystalline silicon is very high, e.g. up to 2×
10−5
Q−cm
2
.
(2) Device circuit performance is not improved due to the high contact resistance, etc.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device with reduced contact resistance between the reaction barrier layer and the polycrystalline silicon in the metal/reactionbarrier/polycrystalline silicon-stacked structure, and a process for producing the same.
The present invention provides a semiconductor device with an MOS transistor, wherein the gate electrode of the MOS transistor is in a stacked structure comprising a silicon layer, a metal silicide layer, a reaction barrier layer such as a metal nitride layer and a metallic layer formed in this order from the bottom upwards.
The present invention also provides a process for producing a semiconductor device, which comprises a step of forming a first insulation layer on the surface of a semiconductor substrate, a step of depositing a silicon layer, on the first insulation layer, a step of depositing a first metallic layer on the silicon layer, a step of depositing a reaction barrier layer such as a metal nitride layer on the first metallic layer, a step of depositing a second metallic layer on the metal nitride layer, a step of processing the stacked structure comprising the silicon layer, the first metallic layer, the metal nitride layer and the second metallic layer into a gate electrode form, a step of ion implanting an impurity onto the surface of the semiconductor substrate, using the gate electrode as a mask, and a step of reacting the first metallic layer with the silicon layer by heat treatment, thereby forming a metal silicide layer.
REFERENCES:
patent: 6265297 (2001-07-01), Powell
patent: 6291868 (2001-09-01), Weimer et al.
patent: 6306743 (2001-10-01), Lee
patent: 2002/0008294 (2002-01-01), Hayashi et al.
Ohnishi Kazuhiro
Yamamoto Naoki
Antonelli Terry Stout & Kraus LLP
Renesas Technology Corp.
Tran Mai-Huong
LandOfFree
Stacked gate electrode for a MOS transistor of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stacked gate electrode for a MOS transistor of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked gate electrode for a MOS transistor of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3340354