Transistor configuration with a shielding electrode outside...

Details Transistor configuration with a shielding electrode outside... Transistor configuration with a shielding electrode outside...

2003-03-19

2004-02-10

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S386000, C257S659000

Reexamination Certificate

active

06690062

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a transistor configuration having at least one active cell array, which is formed from at least one transistor cell configured in a substrate. The transistor configuration has an edge region that surrounds the active cell array at least in sections. The substrate has a substrate surface and a substrate rear side located opposite to the substrate surface, parallel to the substrate surface. The transistor cell has a gate electrode that is electrically insulated from the substrate by an insulator layer. The edge region has an electrically conductive edge gate structure connected to the gate electrode. A drain zone is provided in the substrate and is electrically conductively connected to a drain metallization of the transistor configuration.
In particular, the invention is beneficial in transistor configurations, such as trench MOS (Metal Oxide Semiconductor) power transistors, for instance, which make it possible to control switching currents with high current intensities (up to tens of amperes) by using control voltages in the region of a plurality of volts, in which case the dielectric strength in the switched load circuit may amount to as much as hundreds of volts and the switching times are usually less than one microsecond.
A trench MOS power transistor usually includes a semiconductor body having an active cell array and a passive edge region. A plurality of trench transistor cells are configured one beside another and are electrically connected in parallel in the active cell array.
Depending on the construction of the trench transistor cells, it is possible to realize, for example, normally on and normally off p-channel and n-channel trench MOS power transistors.
FIG. 2
is a simplified cross sectional view of an individual conventional trench transistor cell
3
of a normally off n-channel trench MOS power transistor
1
. In this case, a semiconductor substrate of the trench MOS power transistor
1
includes a heavily n-doped (n++-doped) basic substrate, which forms a drain zone
16
. Configured on the drain zone
16
is a weakly n-doped (n−-doped) drift zone
24
that has emerged from an epitaxial method.
The drift zone
24
is adjoined by first, p-doped and second, n++-doped diffusion regions. In this case, the p-doped diffusion regions form channel zones
27
and the n++-doped diffusion regions form source zones
26
of the trench transistor cell
3
. A trench
9
is provided in the diffusion regions. The inner surface of this trench
9
is lined with a gate oxide
25
. The rest of the trench
9
is filled with conductive polysilicon which forms a gate electrode
10
.
The gate electrode
10
is connected to a gate terminal and the source zones
26
are connected to a source terminal of the trench MOS power transistor. There is provided on the substrate surface
7
a field oxide layer
18
, which electrically insulates the source zones
26
and the gate electrode
10
from applied metallizations. On a substrate rear side
8
located opposite to the substrate surface
7
, a drain metallization
15
is configured adjoining the drain zone
16
of the semiconductor body.
In the zero-voltage state, the conductive source zones
26
are isolated from the drain zone
16
by the p-doped channel zones
27
. If the gate electrode
10
is biased with a positive potential, then minority carriers, in this case electrons, accumulate in the channel zone
27
, directly adjoining the gate oxide
25
. As the positive bias of the gate electrode
10
rises, an n-conducting channel forms in the originally p-conducting channel zone
27
(inversion).
As the current intensity rises between the source zone and the drain zone, the temperature of the semiconductor body increases and the mobility of the charge carriers in the channel zone decreases. This effect means that trench transistor cells can be electrically connected in parallel in a simple manner. By way of example, if a somewhat higher current initially flows through one of the parallel-connected trench transistor cells in the switched-on state, then this leads to a greater temperature increase in this trench transistor cell. On account of the increased temperature, the mobility of the charge carriers in the channel is reduced and the trench transistor cell therefore acquires a higher resistance. Consequently, the current is distributed between cooler trench transistor cells connected in parallel.
In the semiconductor body of a trench MOS power transistor, a trench transistor cell usually includes an elongate trench. In the manner described above, it is possible, then, to arrange a plurality of these trenches one beside the other to form an active cell array.
The maximum current intensity which can be switched by a trench MOS power transistor is determined by the drain-source resistance (RDS(ON)) of the trench transistor cells connected in parallel. The minimum switching time or maximum operating frequency is essentially determined by the gate parameters of input resistance (RG) and input capacitance (CISS).
The input resistance is essentially determined by the resistance of the gate electrodes in the trenches. Added to this is a smaller proportion, resulting from the resistance of the connecting lines between a gate terminal of the trench MOS power transistor and the gate electrodes in the trenches. The input capacitance CISS results from adding the gate-source capacitance (CGS) and the gate-drain capacitance (CGD).
A configuration for trench transistor cells of the kind disclosed in
FIG. 2
has a high capacitance between the gate electrodes
10
and the drift zone
24
assigned to the drain terminal. It results from the fact that the drift zone
24
and the gate electrodes
10
are located opposite one another at the thin gate oxide
25
.
International Publication WO 98/02925 (Franke et al.) discloses a MOS power transistor having a gate electrode configured in a planar manner above the substrate surface. In this transistor, the switching times and switching losses are reduced because of a reduced gate-drain capacitance CGD. In this case, a field electrode connected to the source terminal of the MOS power transistor is respectively configured beside the gate electrode. The field electrode shields the electrical charge on the gate electrode from the drift zone and reduces the area at which the gate electrodes and the drift zone are located opposite one another.
Furthermore, U.S. Pat. No. 5,283,201 (Tsang et al.) discloses a trench MOS power transistor having a gate electrode configured in trenches in a semiconductor substrate. A further region made of the material of the gate electrode is configured below the gate electrode, and this region is electrically insulated from the gate electrode.
By means of concepts of the kind thus disclosed in U.S. Pat. No. 5,283,201 (Tsang et al.) for example, and also by means of a further miniaturization of the structures in the active cell array, it is possible to reduce the switching times and thus also the electrical switching losses that occur during the switching times in the active cell array of MOS power transistors.
Since the switching losses reduce the effectiveness of circuits having MOS power transistors, for instance motor controllers or voltage converters, there is generally a demand for MOS power transistors having further improved switching properties and further reduced switching losses.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a transistor configuration which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is object of the invention to provide a transistor configuration having a reduced gate-drain capacitance in order to obtain an improved switching behavior compared with conventional transistor configurations.
With the foregoing and other objects in view there is provided, in accordance with the invention, a transistor configuration including: a substrate; at least one act

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