Multiplex communications – Pathfinding or routing
Reexamination Certificate
1999-08-19
2004-02-03
Rao, Seema S. (Department: 2666)
Multiplex communications
Pathfinding or routing
C370S401000, C370S489000, C370S502000, C710S008000, C710S062000, C710S311000, C710S312000, C710S313000, C710S316000
Reexamination Certificate
active
06687240
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to information processing systems and more particularly to an improved information transfer system in a computer related environment.
BACKGROUND OF THE INVENTION
As computer systems and networked computer systems proliferate, and become integrated into more and more information processing systems which are vital to businesses and industries, there is an increasing need for faster information processing and increased data handling capacity. Even with the relatively rapid state-of-the-art advances in processor technology, and the resulting increased processor speeds, a need still exists for faster processors and increased system speeds and bandwidths. As new applications for computers are implemented, new programs are developed and those programs are enriched with new capabilities almost on a daily basis. While such rapid development is highly desirable, there is a capability cost in terms of system speed and bandwidth.
As used herein, the term “bandwidth” is used generally to refer to the amount of information that can be transferred in a given period of time. In transferring information between devices in a computer system, information is frequently temporarily stored in “holding” buffers along the path of the information transfer. Such buffers include bridge buffers which are generally located in bridge circuits connecting devices or busses between which the information is to be transferred. In one example, peripheral component interconnect or “PCI” system bridge circuit buffers are assigned to PCI devices, which are installed in PCI “slots” and coupled to an associated PCI bus. Complex computer systems may include many bridge circuits connected between individual PCI busses or connecting a PCI bus to a system bus. In a PCI system, any of the computer system enhancement devices or adapters are generally included on one or more circuit boards which are mounted or inserted into PCI “slots”, i.e. into board connector terminals mounted on a system motherboard.
Standard PCI-PCI bridges are utilized in the industry today as a means to provide added slots for PCI devices since individual PCI busses are limited to 10 loads per bus at 33 MHz and 5 loads at 66 MHz (a soldered device counts as one load and a slotted device counts as two loads). This requires a combination of multiple PCI host bridges and/or multiple standard PCI-PCI bridges per each server drawer where server drawers typically house 14-16 PCI slots per drawer. The total integrated circuit (IC) or chip and packaging cost is expensive utilizing standard components.
Thus, there is an increasing need for an improved computer system which is designed to be able to efficiently handle greater numbers of peripheral adapters in computer systems.
SUMMARY OF THE INVENTION
A method and implementing system is provided in which multiple PCI busses are managed through a combination multiple node PCI-to-PCI bridge including a non-blocking PCI Router (PCIR) circuit. An exemplary embodiment provides a methodology and means for supporting peer-to-peer and IOP transactions between secondary PCI nodes and also means for supporting multiple address spaces for outbound or away-from-processor transactions, utilizing transaction routing tables.
REFERENCES:
patent: 5884027 (1999-03-01), Garbus et al.
patent: 5913045 (1999-06-01), Gillespie et al.
patent: 6145039 (2000-11-01), Ajanovic et al.
patent: 6421755 (2002-07-01), Rao
patent: 6480917 (2002-11-01), Moertl et al.
Moertl Daniel Frank
Neal Danny Marvin
Thurber Steven Mark
Yanes Adalberto Guillermo
Hom Shick
International Business Machines - Corporation
McBurney Mark E.
Rao Seema S.
Wilder Robert V.
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