Logic optimization for preferential shields

Details Logic optimization for preferential shields Logic optimization for preferential shields

2001-11-30

2004-02-03

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06687886

ABSTRACT:

BACKGROUND OF INVENTION
A typical computer system has at least a microprocessor and memory. The microprocessor processes, i.e., executes, instructions to accomplish various tasks of the computer system. Such instructions, along with the data required by the microprocessor when executing these instructions, are stored in some form of memory.
FIG. 1
shows a typical computer system having a microprocessor (
10
) and some form of memory (
20
). The microprocessor (
10
) has, among other components, a central processing unit (also known and referred to as “CPU” or “execution unit”) (
12
) and a memory controller (also known as “load/store unit”) (
14
). The CPU (
12
) is where the actual arithmetic and logical operations of the computer system take place. To facilitate the execution of operations by the CPU (
12
), the memory controller (
14
) provides the CPU (
12
) with necessary instructions and data from the memory (
20
). The memory controller (
14
) also stores information generated by the CPU (
12
) into the memory (
20
).
The operations that occur in a computer system, such as the logical operations in the CPU and the transfer of data between the CPU and memory, require power. If the components responsible for carrying out specific operations do not receive adequate power in a timely manner, computer system performance is susceptible to degradation. As an added challenge, power consumption of modern computers has increased as a consequence of increased operating frequencies. Thus, providing power to the components in a computer system in a sufficient and timely manner has become an issue of significant importance.
Often, power supplied to a computer system component varies, which, in turn, affects the integrity of the component's output. Typically, this power variation results from the distance between a power supply for the component and the component itself. This distance may lead to the component not receiving power (via current) at the exact time it is required. One approach used by designers to combat this performance-inhibiting behavior is introducing decoupling capacitance (also referred to as “decap”) to a particular circuit by positioning one or more decoupling capacitors close to the component. These decoupling capacitors store charge from the power supply and distribute the charge to the component when needed. For example, if power received by a component from a power supply attenuates, one or more decoupling capacitors will distribute charge to the component to ensure that the component is not affected by the power variation on the power supply. In essence, a decoupling capacitor acts as a local power supply for one or more specific components in a computer system.
Within a computer system component, such as a circuit, there are two types of decoupling capacitance: implicit and explicit. Explicit decoupling capacitance is provided to the circuit through the use of decoupling capacitors as discussed above. Implicit decoupling capacitance (also known in the art as “parasitic capacitance” or “inherent capacitance”) is capacitance that is inherent in a circuit. Implicit decoupling capacitance results from the electromagnetic effects between current-carrying wires. Further, implicit decoupling capacitance is a function of the distance between two such wires. Also, the ability to help supplement an attenuating voltage using explicit decoupling capacitors or implicit decoupling capacitance is a function of the potential applied to the decaps.
FIG. 2
shows the presence of explicit and implicit decoupling capacitance in a section of a typical computer system component (
40
). The component (
40
) has a power supply bus (
44
) and a ground bus (
46
) that provides power through a connection to a power supply (
42
). The power supply (
42
) may be a part of the component (
40
) or a separate element. Power from the power supply (
42
) is made available to multiple power supply lines (
48
) and (
52
) via connections to the power supply bus (
44
) and to multiple ground lines (
50
) and (
54
) via connections to the ground bus (
46
). Power from the power supply (
42
) is delivered to chip logic circuits (
60
) and (
68
) via the power supply lines (
48
) and (
52
), respectively, and ground lines (
50
) and (
54
), respectively. When there is power variation across the power supply (
42
), explicit decoupling capacitors (
56
), (
57
), (
58
), and (
59
) positioned in parallel with the power supply (
42
) provides charge, i.e., power, to the chip logic circuits (
60
) and (
68
).
Still referring to
FIG. 2
, the existence of implicit decoupling capacitances (
64
), (
66
), (
72
), and (
74
) is shown. A first occurrence of implicit decoupling capacitance (
64
) occurs between the power supply line (
48
) and a signal line (
62
) from the chip logic (
60
). A second occurrence of implicit decoupling capacitance (
66
) occurs between the signal line (
62
) and the ground line (
50
). The implicit decoupling capacitances (
64
) and (
66
) are dependent on the characteristics of the signal line (
62
), specifically, whether a signal on the signal line (
62
) is high or low. When the signal is low, the implicit decoupling capacitance provided to the chip logic (
60
) is equal to the implicit decoupling capacitance (
64
) between the power supply line (
48
) and the signal line (
62
). Alternatively, when the signal is high, the implicit decoupling capacitance provided to the chip logic (
60
) is equal to the implicit decoupling capacitance (
66
) between the signal line (
62
) and the ground line (
50
).
Still referring to
FIG. 2
, implicit decoupling capacitance is also present in a substantial number of additional circuits. For example, another first occurrence of implicit decoupling capacitance (
72
) occurs between the power supply line (
52
) and a signal line (
70
) from the chip logic (
68
). Another second occurrence of implicit decoupling capacitance (
74
) occurs between the signal line (
70
) and the ground line (
54
). The implicit decoupling capacitances (
72
) and (
74
) are dependent on the characteristics of the signal line (
70
), specifically, whether a signal on the signal line (
70
) is high or low. When the signal is low, the implicit decoupling capacitance provided to the chip logic (
68
) is equal to the implicit decoupling capacitance (
72
) between the power supply line (
52
) and the signal line (
70
). Alternatively, when the signal is high, the implicit decoupling capacitance provided to the chip logic (
68
) is equal to the implicit decoupling capacitance (
74
) between the signal line (
70
) and the ground line (
54
).
SUMMARY OF INVENTION
According to one aspect of the present invention, a method for preferentially shielding a plurality of signal paths where each of the plurality of signal paths has a value switchable between a first potential and a second potential comprises determining a probability for each of the plurality of signal paths that the value will be at the first potential versus the second potential, assigning a shield to each of the plurality of signal paths where each shield is assigned a potential based upon the probability of the corresponding signal path, determining if an imbalanced state exists among the shields, and if the imbalanced state exists, inverting the value of one of the signal paths to reduce the imbalanced state.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 5027321 (1991-06-01), Park
patent: 6229095 (2001-05-01), Kobayashi
patent: 6353917 (2002-03-01), Muddu et al.
patent: 6510545 (2003-01-01), Yee et al.
patent: 0575892 (1993-12-01), None
Chhal et al., “A Novel Integrated Decoupling Capacitor For MCM-L Technology ”, IEEE, May 1988, PP. 184-193.*
Notification of Transmittal of the International Search Report or the Declaration dated May 7, 2003 (2 pages).

Affiliated with

Also associated with

Rating

Logic optimization for preferential shields does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Logic optimization for preferential shields, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic optimization for preferential shields will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3340095