Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-06-28
2004-11-16
Vo, Don N. (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
Reexamination Certificate
active
06819727
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field Of The Invention
The present invention relates to a method and device for the numeric control of the buffer and of a phase-locked loop for asynchronous networks.
2. Background Information
Real time transmission of signals (such as e.g. speech or video signals) through asynchronous networks requires the use of sophisticated buffer control and clock recovery techniques. For instance, communication networks based on packet switching, such as the ATM (Asynchronous Transfer Mode), introduce, at the receive side, a remarkable amount of jitter, just due to the asynchronous nature of the transmission and to delay uncertainties introduced by the network nodes: the typical patterns of such uncertainties are generally known but the related statistical parameters are not.
In order to recover the source sync signal, it is known to use phase-locked loops (PLLs), possibly digital phase-locked loops (DPLLs), along with a buffer for storing the received data to be de-jittered.
A conventional method consists in writing data into memory (buffer), keeping trace of the filling level thereof and locking the PLL to the latter.
For high jitters, it is known to use the technique of the so-called time-stamps, i.e. time information that is periodically transmitted by the transmitter to the receiver(s) along with the useful information (i.e. the payload): such time information, properly processed by the DPLL, hence allows the reconstruction of the signal at the receive side by locking a local clock thereto thus realizing a remote “synchronization”. There are, on the other hand, applications in which the time-stamps are not transmitted or are not usable even if transmitted by the source; in fact they are calculated in relation to a frequency, well known at trasmission side, that has to be sent to the receiver: if the latter is not received, the time information is totally useless.
Therefore, the main object of the present invention is to provide a method and device for the numeric control of the buffer and of a phase-locked loop for asynchronous networks capable of overcoming the above drawbacks. In particular, the new method as proposed herein proves to be very useful in those applications where time-stamps are not transmitted or could not be used.
Anyway, it is necessary to provide a buffer control algorithm in order to avoid both the loss of data, if the amount of these exceeds its maximum capacity (overflow), and the lack of data to be supplied to the receiving system if the buffer is empty (underflow).
SUMMARY OF INVENTION
Therefore, the present invention provides a method for the digital control of the buffer which, possibly associated with a digital phase-locked loop, for instance the one covered by a previous patent-right belonging to the same applicant, is able to overcome the above-mentioned drawbacks; particularly, but not exclusively, it provides for an improvement in the performances of the synchronizing block in terms of buffer use optimization, a reduction in the probabilities of overflow and underflow and an excellent jitter rejection even at very-low frequencies.
In order to achieve these objects, the present invention provides a method for the buffer numeric control.
The present invention provides also a device for the numeric control of the buffer.
The present invention further provides a phase-locked loop.
The basic idea of the present invention consists in introducing a buffer which can be termed “virtual” (or addressed using a “virtual pointer”) for managing the buffer control system and a loop which provides a digital phase-locking on a statistical basis rather than by means of the actual measure of the input phase.
Among the advantages of the present invention there is the enhancement of the buffer performances while reducing the overflow and underflow probabilities and the increase of the frequency stability of the recovered clock signal.
Further objects and advantages of the present invention will result in being clear from the following detailed description of an embodiment thereof and from the accompanying drawings attached merely by way of illustration and not of limitation.
REFERENCES:
patent: 4827225 (1989-05-01), Lee
patent: 5402425 (1995-03-01), Bladh
patent: 5526362 (1996-06-01), Thompson et al.
patent: 6118834 (2000-09-01), Rasanen
patent: 6252850 (2001-06-01), Lauret
Cucchi Silvio
Meli Daniele
Alcatel
Vo Don N.
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