Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-17
2004-08-17
Nguyen, Cuong (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S750000, C257S758000
Reexamination Certificate
active
06777738
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit and a manufacturing method thereof, and particularly to a semiconductor integrated circuit including a conductive plug in a contact hole formed in an insulating film provided on a substrate and a manufacturing method thereof.
2. Description of the Background Art
With the increased level of integrated of a semiconductor integrated circuit, the width of an interconnection wiring and the size of a contact hole have been reduced. A method has been known for connecting a lower interconnection layer or a semiconductor substrate to an upper interconnection layer via a contact hole, wherein a metal film is formed in the contact hole by sputtering. However, it is difficult to form such a metal film in a fine contact hole with a sufficient coverage by sputtering. For a semiconductor integrated circuit including a fine contact hole, therefore, a plug technique has been generally used in which a high melting point metal film made from tungsten (W) or the like is formed in a wide region containing the contact hole by CVD and then a metal film is selectively formed in the contact hole by etching-back.
A related art method of manufacturing a semiconductor integrated circuit using the above plug technique will be described below with reference to
FIGS. 10
to
16
. In these figures, like or corresponding parts are designated by like reference numerals and explanation thereof is omitted.
In accordance with the related art manufacturing method, as shown in
FIG. 10
, oxide isolation regions
2
, a gate electrode
3
and source/drain regions
4
of each transistor, and a first interlayer insulating film
5
are formed in or on a semiconductor substrate
1
. A first contact hole
6
communicated to one source/drain region
4
is formed in the first interlayer insulating film
5
. A metal film is formed on the surface of the first interlayer insulating film
5
in such a manner as to fill the first contact hole
6
. The metal film is then patterned by photolithography and etching, to form a first interconnection layer
7
.
Referring to
FIG. 11
, a second interlayer insulating film
8
is formed in such a manner as to cover the first interconnection layer
7
. A second contact hole
9
is formed in such a manner as to be opened to the other source/drain region
4
through the second interlayer insulating film
8
. A polysilicon layer is formed over the entire surface of the semiconductor substrate
1
, and patterned by photolithography and etching to form a charge storage node
10
(hereinafter, referred to as “storage node
10
”).
A third insulating film
11
is thinly formed in such a manner as to cover the storage node
10
. Then, a polysilicon layer is formed again on the third insulating film
11
. The polysilicon layer is patterned by photolithography and etching, to form an upper electrode
12
for storage of charges (hereinafter, referred to as “cell plate
12
”). The storage node
10
, the third insulating film
11
, and the cell plate
12
constitute a capacitor functioning as a memory cell.
The amount of charges allowed to be stored in the capacitor is proportional to the surface area of the storage node
10
, and inversely proportional to the thickness of the third insulating film
11
. As the device structure becomes finer, the area on the substrate which is allocated to the storage node
10
becomes smaller. Accordingly, in general, to ensure the necessary charges allowed to be stored in the capacitor, the thickness of the third insulating film
11
is made thin and the height of the storage node
10
is made large.
Referring to
FIG. 12
, a fourth interlayer insulating film
13
and a fifth interlayer insulating film
14
are sequentially formed over the entire surface of the semiconductor substrate
1
in such a manner as to cover the cell plate
12
. The first, second, fourth and fifth interlayer insulating films
5
,
8
,
13
and
14
are selectively removed by photolithography and etching, to form a third contact hole
15
which is opened through the above films to the source/drain region
4
of a transistor separated from the above transistor by the oxide isolation region
2
.
The region on the semiconductor substrate
1
is separated into a capacitor region in which the capacitor is to be formed (hereinafter, referred to as “memory cell region”) and a peripheral circuit region in which a peripheral circuit is to be formed. A surface stepped portion stemming from the storage node
10
is formed between the memory cell region and the peripheral circuit region. If the surface stepped portion is larger than the focal depth upon photolithography, a failure in resolution of a resist pattern may easily occur. Also upon etching of high melting point metal films to be described later, as the surface stepped portion becomes larger, an etching residue remains easier on the stepped portion, leading to an electric short-circuit failure. Further, as the height of the storage node
10
becomes larger, the problem due to the surface stepped portion becomes more serious.
To suppress occurrence of the above-described problem, the fourth interlayer insulating film
13
is usually configured as a BPSG (Boro-Phospho Silicate Glass) film. BPSG film has a property that being softened and planarized at a high temperature of 800° C. or more to make the surface thereof into a smooth flow shape. The use of the BPSG film as the interlayer insulating film is effective to easily suppress the surface stepped portion of the device. The planarization characteristic of the BPSG film is dependent on the concentrations of boron (B) and phosphorus (P). To be more specific, as the concentrations of B and P become higher, the planarization characteristic of the BPSG film becomes more desirable.
The quality of the BPSG film containing B and P at high concentrations is generally unstable, and more specifically, it is liable to be changed depending on moisture absorption and the like. Further, since the BPSG film is poor in adhesion with a resist used for photolithography, there occurs a problem that when a resist pattern is directly formed on the BPSG film, the resist pattern may be peeled therefrom. For this reason, as described above, the insulating film having the double layer structure of the fourth interlayer insulating film (BPSG film)
13
for ensuring planarization between the memory cell region and the peripheral circuit region and the fifth interlayer insulating film
14
formed on the fourth interlayer insulating film
13
to a thickness ranging from several tens to several hundreds nm is provided on the cell plate
12
.
After removal of the resist pattern used as a mask upon selective etching for forming the third contact hole
15
, the semiconductor substrate
1
is generally subjected to wet cleaning using a NH
4
OH/H
2
O
2
solution or the like for removing foreign matters remaining on the wafer surface. At this time, the surface of the fifth interlayer insulating film
14
is etched to about several tens nm and also a portion, exposed as the inner wall of the third contact hole
15
, of the fourth interlayer insulating film
13
is etched.
Upon etching using the NH
4
OH/H
2
O
2
solution for wet cleaning, the etching rate for the fourth interlayer insulating film
13
containing B and P is larger than that for the fifth interlayer insulating film
14
. Accordingly, by the above-described wet cleaning, irregularities shown in
FIG. 12
are formed on the inner wall of the third contact hole
15
. The irregularities formed on the inner wall of the contact hole
15
can be somewhat suppressed by shortening the cleaning time; however, if the cleaning time is shortened, there occurs a problem in degrading the effect of removing foreign matters thereby reducing the manufacturing yield.
Referring to
FIG. 13
, a first high melting point metal film
16
is formed by sputtering or the like in such a manner as to cover the inner wall of the third contact hole
15
and the surface
Nguyen Cuong
Renesas Technology Corp.
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