Method for generating register transfer level code

Details Method for generating register transfer level code Method for generating register transfer level code

2002-08-23

2004-02-24

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C703S015000, C703S022000

Reexamination Certificate

active

06698001

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for generating a register transfer level (RTL) code for a very large scale integrated circuit VLSI design.
DESCRIPTION OF THE RELATED ART
Generally, numerous logic circuits are integrated into a single chip by a very large scale integrated circuit VLSI technology. Due to the increased number of logic circuits comprising the highly integrated circuit, however, each logic circuit cannot be designed separately by programmers. Therefore, a timing delay in each logic circuit and a timing error can be occur when numerous logic circuits are integrated in a short period of time.
In order to solve the above problem, a RTL code, which can change process conditions of each logic circuit consisting of the VLSI, is introduced. However, if the number of logic circuits comprising the VLSI is increased, the length of the RTL code is increased, which reduces the recognition of the RTL code. Therefore, this method is not the proper solution as is the case with core logic.
FIG. 1
is a general circuit diagram of a method for generating an ordinary RTL code in accordance with the present invention.
Referring to
FIG. 1
, the circuit includes two AND gates
10
and
20
, an OR gate
30
, a D flip-flop
40
and a three-state buffer
050
. The circuit in
FIG. 1
can be described in RTL as shown in Table 1. The first AND gate
10
is expressed as (a) in Table 1 so that an AND gate AND
02
D
1
, which is verified in a certain process condition, is used by the first AND gate
10
. Herein, signals A and B are inputted to the first AND gate
10
and a signal E is outputted from the first AND gate
10
. The second AND gate
20
is expressed as (b) in Table 1 so that an AND gate AND
02
D
2
, which is verified in a certain process condition, is used by the second AND gate
20
. Herein, signals C and D_L
1
are inputted to the second AND gate
20
and a signal F is outputted from the second AND gate
20
.
The terms “and
2
_
0
” and “and
2
_
1
” in Table 1 are called “instance” and they are expressions for distinguishing each AND gate. That is, designing the VLSI by the instance distinguishes the first and second AND gates and
2
_
0
and and
2
_
1
.
The D flip-flop
40
is described as (c) in Table 1. The D flip-flop
40
receives a signal D and a clock signal CLK
1
and outputs the signal D_L
1
, which is a signal D synchronized with the clock CLK
1
. In the OR gate
30
, a verified device OR
02
D
2
is employed as the tool for designing the VLSI and signals E and F are inputted thereto and a signal 01_T is outputted. The three-state buffer
50
is described as (e) in Table 1 and the signal O
1
_T is inputted thereto and a signal O
1
is output ed. The three-state buffer
50
is controlled by an enable signal O
1
_E.
In the OR gate
30
, a verified device OR
02
D
2
is employed as the tool for designing the VLSI so that E and F become input terminals and “O
1
_T” becomes an output terminal.
The three-state buffer
50
is described as (e) in Table 1 so that “O
1
_OE” becomes an input terminal and “O
1
_T” becomes an output terminal. At this point, the three-state buffer
50
is controlled by a signal applied from a terminal O
1
in order to output an output signal.
TABLE 1
(a)
AND02D1 and2_0(.Al(A), .A2(B), .Z(E));
(b)
AND02D2 and2_1(.Al(C), .A2(D), .Z(F));
(c)
DFF dff_0(.clk(CLK1), .D(D), .Q(D_L1));
(d)
OR02D1 or2_0 (.A1(E), A2(F), .ZN(O1_T));
(e)
TRB1 trb1_1(.OE(O1_OE), .I(O1_T), .(O1));
The description for writing each logic circuit can be varied depending on the tool and its version.
In the prior art, the RTL code is employed in consideration of the timing delay and error. Separate delay time, timing and process conditions are required in the compilation in order that the D flip-flop
40
and the three-state buffer
50
are configured to a hardware with all logic gates
10
to
50
composing the logic circuit.
If the process condition, such as width of metal line, current capacity of device and driving capability of the integrated circuit is changed, AND gates
10
and
20
and the OR gate
30
in the RTL code, which is written in a register transfer level code, must be changed.
Therefore, the RTL code has to be re-written with respect to the process condition if the existent circumstances, where hundreds of thousands of core logics are integrated, are to be taken into consideration.
Furthermore, when the VLSI having over hundreds of thousands gates is designed by the conventional register transfer level, the length of the RTL code is exceedingly increase so that a lot of time is required to change the process conditions being in the TRL code and, when a certain error is found and th n corrected, it is difficult that a programmer recognizes the error.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for generating a register transfer level code.
In accordance with an aspect of the present invention, there is provided a method for generating a register transfer level code, comprising the steps of: generating the generalized register transfer level code without considering the process conditions; separating all logic gates into either a combinational logic circuit or a sequential logic circuit; transforming the register transfer level code of the separated combinational logic circuits and sequential logic circuits into each equivalent register transfer level code; and simplifying the combinational logic circuits and the sequential logic circuits into one simple code.
In accordance with another aspect of the present invention, there is provided a storage media for executing a method for generating a register transfer level code, comprising instructions performing the steps of: generalizing each register transfer level code of a combinational logic circuit and a sequential logic circuit; separating the register transfer level codes of the generalized combinational logic circuit and the sequential logic circuit; transforming the register transfer level code of the separated combinational logic circuits and sequential logic circuits into each equivalent register transfer level code; and simplifying the combinational logic circuits and the sequential logic circuits into one simple code.
In accordance with still another aspect of the present invention, there is provided a storage media for executing a method for generating a register transfer level code in a logic circuit having a three-state buffer, comprising instructions performing the steps of: generating the generalized register transfer level code without considering the process conditions; separating all logic gates into either a combinational logic circuit or a sequential logic circuit; transforming the register transfer level code of the separated combinational logic circuits and sequential logic circuits into each equivalent register transfer level code; and simplifying the combinational logic circuits and the sequential logic circuits into one simple code.


REFERENCES:
patent: 2001/0011212 (2001-08-01), Raynaud et al.
patent: 2002/0174409 (2002-11-01), Cohn et al.
patent: 2003/0061573 (2003-03-01), Tsuchiya
patent: 2000-41368 (2000-07-01), None

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