Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-10-15
2004-06-22
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C709S208000, C709S209000, C709S210000, C709S211000, C710S001000, C710S317000, C711S111000, C711S112000, C711S167000
Reexamination Certificate
active
06754769
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a disk array controller and a method of controlling disk array, in particular to the disk array controller and the method of controlling disk array, each of which is characterized in controlling data transfer between a host computer and disk devices.
A conventional disk array controller (hereunder called a first prior art) comprises host computer adapters each of which is connected to each host computer and which carry out data transfer, a cache memory which temporarily memorizes not only data transmitted from host computers and disk enclosures but also information for controlling the disk array controller, and disk enclosure adapters each of which is connected to each disk enclosure and which carry out data transfer. The host computer adapters, the disk enclosure adapters, and the cache memory are multi-connected to each other through a common bus. All of the data transfer is carried out by way of the cache memory.
In the first prior art, transfer performance is improved by enlarging bus width of the internal common bus and fastening transfer period of the internal common bus. However, a structure of a conventional common bus cannot catch up with improvement of performance of a host computer interface and a disk enclosure interface in the first prior art. In addition, reflection of signal wave is inevitably caused to occur due to the structure of the conventional common bus. Accordingly, it has become difficult to respond to a requirement for obtaining a disk array controller having high performance.
On the other hand, as a proposal for solving such a problem of the conventional disk array controller, for example, unexamined Japanese Patent Publication 2000-99281 discloses an another conventional disk array controller (hereunder called a second prior art) in which a host computer and a cache memory are connected to each other through a plurality of host computer adapters and in which a disk enclosure and a cache memory are connected to each other through a plurality of disk enclosure adapters. In this second prior art, fault-proof capability and a throughput of the disk array controller are improved to some extent by transferring data through a plurality of adapters. However, it has a limit to improve the throughput even in the second prior art thus mentioned.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a disk array controller and a method of controlling disk array which are capable of further improving the throughput in the disk array controller.
Other objects of the present invention will become clear as the description proceeds.
According to an aspect of the present invention, there is provided a disk array controller for use in storing data transmitted and received between a host computer and a disk enclosure, comprising: at least one cache memory which stores the data transmitted and received between the host computer and the disk enclosure; the at least one cache memory including at least one memory module and a plurality of crossbar switches connected with the at least one memory module; a plurality of host computer adapters which connect the host computer with the at least one cache memory; a plurality of host computer adapters being connected with a plurality of crossbar switches; a plurality of disk enclosure adapters which connect the disk enclosure with the at least one cache memory; a plurality of disk enclosure adapters being connected with a plurality of crossbar switches; and a plurality crossbar switches have function to directly connect the host computer adapters to the disk enclosure adapters.
Each of a plurality of crossbar switches may directly connect each of the host computer adapters to each of the disk enclosure adapters in response to a command outputted from each of the host computer adapters.
The crossbar switches may transfer data in synchronization with each other.
One of a plurality of crossbar switches may be operable as a master while the others of a plurality of crossbar switches may be operable as a slave controlled by the master, so that a plurality of crossbar transfer data in synchronization with each other.
Each of a plurality of crossbar switches may have a buffer memory for temporarily storing data transmitted from the host computer adapters or the disk enclosure adapters.
The data transmitted from the host computer adapters or the disk enclosure adapters may include a command and a memory address, the data including the command and the memory address being collectively transmitted to the buffer memory.
According to another aspect of the present invention, there is also provided a disk array controller for use in storing data transmitted and received between a host computer and a disk enclosure, comprising: at least one cache memory which stores the data transmitted and received between the host computer and the disk enclosure; the at least one cache memory including at least one memory module and a plurality of crossbar switches connected with the at least one memory module; a plurality of host computer adapters which connect the host computer with the least one cache memory; a plurality of host computer adapters being connected with a plurality of crossbar switches; a plurality of disk enclosure adapters which connect the disk enclosure with the at least one cache memory; a plurality of disk enclosure adapters being connected with a plurality of crossbar switches; and a plurality of crossbar switches transferring data in synchronization with each other.
According to still another aspect of the present invention, there is also provided a method of controlling a disk array for use in a disk array controller including at least one cache memory which stored data transmitted and received between a host computer and a disk enclosure, a plurality of host computer adapters which connect the host computer with the at least one cache memory, a plurality of disk enclosure adapters which connect the disk enclosure with the at least one cache memory, the method comprising the steps of providing at least one memory module and a plurality of crossbar switches in the at least one cache memory; connecting a plurality of host computer adapters with a plurality of crossbar switches; connecting a plurality of disk enclosure adapters with a plurality of crossbar switches; connecting a plurality of crossbar switches with the at least on memory module; and directly connecting the host computer adapters to the disk enclosure adapters.
REFERENCES:
patent: 5889969 (1999-03-01), Getzlaff et al.
patent: 6094715 (2000-07-01), Wilkinson et al.
patent: 6578126 (2003-06-01), MacLellan et al.
patent: 6594739 (2003-07-01), Walton et al.
patent: 6611879 (2003-08-01), Dobecki
patent: 10-143465 (1998-05-01), None
patent: 10-171746 (1998-06-01), None
patent: 11-296473 (1999-10-01), None
patent: 2000-99281 (2000-04-01), None
patent: 2000-099281 (2000-04-01), None
patent: 2002-533835 (2002-10-01), None
Japanese Office Action dated Dec. 24, 2002, with partial English translation.
Japanese Office Action dated Apr. 8, 2003 with Partial English Translation.
McGinn & Gibb PLLC
NEC Corporation
Nguyen T
LandOfFree
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