Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-11-03
2004-11-30
Nguyen, Cuong (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S347000, C257S378000
Reexamination Certificate
active
06825524
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based on and claims the benefit of priority from the prior Japanese Patent Application No. 2003-307202, filed on Aug. 29, 2003, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor integrated circuit device. More particularly, the invention relates to a memory device formed on a silicon-on-insulator (SOI) substrate, a channel body of which stores data determined by majority carrier accumulation states.
2. Description of Related Art
Recently, for the purpose of alternative use or replacement of conventional DRAMs, a semiconductor memory device that has a more simplified cell structure for enabling achievement of dynamic storability has been provided. This type memory device is disclosed, for example, in Takashi Ohsawa et al., “Memory Design Using One-Transistor Gain Cell on SOI”, ISSCC Digest of Technical Papers, 2002, pp. 152-153. A memory cell is formed of a single transistor which has an electrically floating body (channel body) as formed on a silicon-on-insulator (SOI) substrate. This memory cell stores two-value data as follows: a first data (for example, logic “1” data) is stored as a state that an excess number of majority carriers are accumulated or stored in the body; and a second data (for example, logic “0” data) is stored as a state that the excessive majority carriers are drawn out from the body.
The memory cell of the type stated above will be referred to hereinafter as a “floating-body cell (FBC)”. A semiconductor memory using FBCs will be referred to as a “FBC memory”. The FBC memory makes use of no capacitors unlike currently available standard DRAM chips so that the memory cell is simpler in memory cell array structure and smaller in unit cell area than ever before. Thus, the FBC memory is readily scalable in cell structure and advantageously offers much enhanced on-chip integration capabilities.
FIG. 24
shows an equivalent circuit of a cell array in the FBC memory.
For writing logic “1” data in the FBC memory, impact ionization near the drain of a memory cell is utilized. More specifically, as shown in
FIG. 25
, giving an appropriate bias condition for permitting flow of a significant channel current in the memory cell, majority carriers (holes in this case) are generated by impact ionization and stored in the floating body. Writing logic “0” data is performed by setting a PN junction between the drain and the body in a forward bias state, as shown in
FIG. 26
, thereby releasing the body's majority carries toward the drain side.
A difference in the carrier storage states of the floating body appears as a difference in threshold voltage of a transistor. Thus, detecting whether an appreciable cell current is present or absent, alternatively, whether the cell current is large or small in magnitude, by applying a read voltage to the gate of a selected memory cell, as shown in
FIG. 27
, it is possible to determine or sense whether the resultant read data is a logic “0” or “1”.
FIG. 28
shows a characteristic of drain current Ids versus gate voltage Vgs of the memory cell with respect to data “0” and “1”.
When letting the body be unprocessed for an increased length of time period, the excessive majority carriers of the body will be drawn out through the PN junctions at the drain and source. Therefore, it is required to perform refresh operations at constant time intervals as in ordinary DRAMs.
To improve the characteristics of the FBC memory, it has also been proposed to employ an auxiliary gate which is capacitively coupled to the floating body in addition to the main gate. This approach is disclosed, for example, in Japanese Patent Application Laid Open No. 2002-246571 (Patent Document 1) and Japanese Patent Application Laid Open No. 2003-31693 (Patent Document 2).
Similar memory devices have been proposed, for example, in U.S. Pat. No. 5,448,513 specification (Patent Document 3), U.S. Pat. No. 5,784,311 specification (Patent Document 4) and U.S. Pat. No. 6,111,778 specification (Patent Document 5). These memory devices have a different write scheme, while employing carrier accumulation in the floating body as similar to the above described FBC memory. That is, these memory cells are formed of a PMOS transistor as a cell transistor and an NMOS transistor for injecting carriers into the floating body of the PMOS transistor. These PMOS and NMOS transistors have a common gate.
It has also been proposed a method of employing a bipolar operation for injecting carriers into a floating body through a tunnel insulating film, for example, in Japanese Patent Application Laid Open No. 5-347419 (Patent Document 6) and U.S. Pat. No. 5,355,330 specification (Patent Document 7).
In the FBC memory devices proposed up to the present, since the impact ionization current is small, it takes a long time for writing data “1”. For reducing the “1” write time, it is desirable to set the bit line voltage (drain voltage) in the “1” write bias condition shown in
FIG. 25
to be more higher, thereby increasing the impact ionization current. Unfortunately, this takes the risk of erroneous write in non-selected cells. This situation will be explained in detail referring to FIG.
29
.
FIG. 29
shows a bias relationship for a selected cell into which “1” data is written and a non-selected cell. When the gate (word line WL) of the non-selected cell is set at −1.5V, &Dgr;V=3V is applied between the gate and drain thereof. Due to this voltage &Dgr;V, gate induced drain leak (GIDL) flows in the drain of the non-selected cell. Setting the bit line voltage to be higher for reducing the “1” write time of the selected cell, the GIDL current becomes large in the non-selected cell. Therefore, when the non-selected cell is held at a “0” data state, “1” data may be erroneously written into it.
Another problem of “1” write by use of impact ionization is in a fact that power consumption is large. Since the “1” write cell operates in a pentode region (current saturation region), a large drain current (channel current) flows therein. The impact ionization current is about 1/10000 times as much as the drain current. Therefore, the drain current serves little for charging the body capacitance, thereby being uselessly consumed. In a case that “1” write is performed for many cells in a chip, the power supply voltage may be reduced due to the entire drain currents to lead to an erroneous operation.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor integrated circuit device including:
a substrate;
a first conductivity type of semiconductor layers arranged above the substrate as being insulated from the substrate and insulated from each other;
cell transistors formed on the respective semiconductor layers, each of which has a second conductivity type of source, drain layers and a gate electrode to store data in a channel body thereof corresponding to an accumulation state of majority carriers; and
the first conductivity type of emitter layers formed in the respective semiconductor layers to be contacted to the respective drain layers of the cell transistors so as to constitute PN junctions therebetween, the emitter layers serving for injecting majority carriers into the respective channel bodies of the cell transistors.
REFERENCES:
patent: 5350938 (1994-09-01), Matsukawa et al.
patent: 5355330 (1994-10-01), Hisamoto et al.
patent: 6653175 (2003-11-01), Nemati et al.
patent: 5-347419 (1993-12-01), None
patent: 2002-246571 (2002-08-01), None
patent: 2003-31693 (2003-01-01), None
T. Ohsawa, et al., “Memory Design Using One Transistor Gain Cell on SOI”, ISSCC Digest of Technical Papers, ISSCC 2002/ Session 9/ Dram and Ferroelectric Memories/9.1, Feb. 2002, pp. 152-153 and 454.
Ikehashi Tamio
Ohsawa Takashi
LandOfFree
Semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3337386