Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2003-04-08
2004-12-28
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S618000, C438S628000, C438S634000, C438S641000, C438S644000
Reexamination Certificate
active
06835652
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dual damascene process. It is particularly related to a method of fabricating a pattern of a via and an interconnective trench with a via-first method, namely by first forming the via so as to connect upper and lower layers with interconnect.
2. Description of the Prior Art
Recently, improvements in performance and function of semiconductor integrated circuits used for electronic information technology devices including mobile phones are well known. The fact that such semiconductor integrated circuit is manufactured with a high-precision semiconductor manufacturing process is also well known. In addition, attention is given to an interconnection structure manufactured with the dual damascene process within the above high-precision semiconductor manufacturing process.
Such dual damascene process is an approach to forming multi-layered interconnection by forming both an interconnective trench, which becomes an upper layer interconnect formed and embedded in an interlayer insulating film, and a via hole, which is used to connect an upper layer interconnect with a lower layer interconnect, and then embedding a metal film in the upper layer interconnect and the lower layer interconnect, simultaneously. There are advantages where semiconductor manufacturing steps may be reduced and manufacturing costs thereof may be greatly reduced in comparison to the process that individually forms a via hole and interconnective trench. Particularly, the via-first method is one dual damascene process that first forms the via hole within the interlayer insulating film, subsequently forming the interconnective trench.
FIG.
1
A through FIG.
1
D and FIG.
2
A through
FIG. 2C
depict a conventional via-first method. To begin with, as illustrated in
FIG. 1A
, an interlayer insulating film
117
is formed by successively layering a silicon dioxide film
113
, an etch stop film
114
, a low-permittivity film
115
and a silicon dioxide film
116
upon a lower layer interconnect
112
formed on an insulating film
111
that is upon a silicon substrate not shown in the drawings with the conventional via-first method.
A via hole
118
, which reaches the lower layer interconnect
112
, is then opened in the interlayer insulating film
117
with photolithography techniques utilizing a photoresist not shown in the drawings. Next, as illustrated in
FIG. 1B
, an anti-reflective coating
119
is applied across the entire interlayer insulating film
117
and baked to harden, whereby the anti-reflective coating
119
is embedded in the via hole
118
up to nearly half its depth with the conventional via-first method. Subsequently, as illustrated in
FIG. 1C
, a chemically amplified positive type resist
121
for patterning is applied. Next, as illustrated in
FIG. 1D
, the positive type resist
121
is exposed into a predetermined pattern and developed so as to form an interconnective trench resist pattern
121
a
. Following as in
FIG. 2A
, an interconnective trench
122
is formed by etching the low-permittivity film
115
and silicon dioxide film
116
upon the etch stop film
114
using the interconnective trench resist pattern
121
a.
Thereafter, upon removal of the anti-reflective coating
119
within the via hole
118
and on the interlayer insulating film
117
as illustrated in
FIG. 2B
, the silicon dioxide film
116
is etched and removed as in FIG.
2
C. Subsequently, a metallic material
123
is embedded in the interconnective trench
122
and via hole
118
, and only the metallic material
123
is left therein using chemical mechanical polishing (CMP). The dual damascene structure that is configured from a via
124
and a trench interconnect (upper layer interconnect)
125
is then completed.
However, the following problems arise with the conventional via-first method. Namely, when forming the interconnective trench resist pattern
121
a
by subjecting the positive type resist
121
to an exposure and a development process as indicated in the procedure of
FIG. 1D
, development using a developing fluid for the positive type resist
121
that is applied in the deep via hole
118
is not adequately performed, whereby a portion of the resist
121
remains in the via hole
118
.
Consequently, forming the interconnective trench
122
by etching the low-permittivity film
115
and silicon dioxide film
116
under these conditions causes etch residue X that is called a crown to generate in the interconnective trench
122
along the remaining resist
121
as in FIG.
2
A. This etch residue X cannot be easily eliminated by an organic stripping solution.
Consequently, as in FIG.
2
B and
FIG. 2C
, the metallic material
123
is embedded in the interconnective trench
122
and via hole
118
thereafter, and moreover, the etch residue X remains until the via
124
and trench interconnect
125
are formed. As a result, electrically discontinuous portions or highly electrical highly resistant portions generate between the via
124
and trench interconnect
125
, and decline in interconnect yield and reliability occurs.
As causes for such crown generation, the following two points can be given. First, since the vial hole is considerably deep, the resist that has penetrated into the via hole is exposed in a nearly 1 mm defocused state when forming the resist pattern of the interconnect trench through exposure. Accordingly, optical power in this area is extremely low, and a high rate of solution can no longer be obtained during development. As a result, resist remains within the via hole.
Second, density of the low-permittivity interlayer insulating film that is used in multilayered interconnections is typically low, and large amounts of moisture and basic impurities are included in the inner portions thereof. Since they diffuse from the via hole into the resist, a chemically amplified reaction is inhibited. Accordingly, the rate of solution of the resist within the via hole further decreases, and residual resist called poisoning and/or poor resolution occur.
Consequently, according to examination by the inventor, with the dual damascene process of the via-first method, the resist left in the via hole must be eliminated. The via-first method in such light is disclosed in Japanese Patent Application Laid-Open No. 2000-195955 (Reference 1).
In Reference 1, material including a thermally cross-linked compound is proposed as the embedding material for filling in the via hole, whereat the given example uses an alkali soluble resin and positive type resist composite as comparative examples. Since these are embedded in a different procedure than that of the resist used for forming the resist pattern for the interconnect trench, a portion of that resist penetrating into the via hole and remaining therein due to development when forming that resist pattern is unavoidable.
SUMMARY OF THE INVENTION
The object of the present invention is to inhibit residual resist in the via hole; and to provide a pattern formation method, which can manufacture a highly reliable dual damascene structure.
A method of fabricating patterns with a dual damascene process of the present invention, including the steps of: opening a via hole in an interlayer insulating film, which covers a lower conductive layer, so as to expose part of the lower conductive layer; embedding a protective film on the base portion of the via hole; embedding a soluble resin, which dissolves in a resist developing fluid under unexposed conditions upon the protective film in the via hole; forming a resist pattern, which has an aperture window in a region including the via hole, by applying a photoresist upon the interlayer insulating film, and subjecting this photoresist to an exposure and a development process; forming an interconnective trench in the surface of the interlayer insulating film utilizing the resist pattern; removing the protective film; and forming a dual damascene structure by embedding a metallic material into the vial hole and interconnective trench.
According to
NEC Electronics Corporation
Perkins Pamela E
Young & Thompson
Zarabian Amir
LandOfFree
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