Static information storage and retrieval – Read/write circuit – Including signal clamping
Reexamination Certificate
2002-09-19
2004-08-17
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including signal clamping
C365S189040, C365S189070, C365S226000
Reexamination Certificate
active
06778446
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to non-volatile semiconductor memory apparatuses, and more particularly to non-volatile semiconductor memory apparatuses equipped with charge pump devices that step up power supply voltage.
2. Description of Related Art
Semiconductor memory apparatuses may be classified into a variety of different types depending on their functions. Such semiconductor memory apparatuses includes a memory cell array that is formed of memory cells arranged in a matrix. In general, an address in a row direction and a column direction in the memory cell array is designated in performing a reading, programming or erasing operation for each of the memory cells.
By controlling voltages applied to a signal line in the row direction and a signal line in the column direction that are connected to each of the memory cells, a specified memory cell can be accessed, such that a specified operation among reading, programming and erasing operations thereof can be performed. In other words, in order to select a specified memory cell, a voltage different from other voltages to be applied to other memory cells may be generated from the power supply voltage and applied.
Recenlty, MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or substrate) type devices have been developed as non-volatile semiconductor devices that are electrically erasable and have non-volatility. A MONOS type non-volatile semiconductor memory apparatus has memory cells that each have two memory elements, as described in detail in a publication (Y. Hayashi, et al, 2000 Symposium on VLSI Technology Digest of Technical Papers p. 122-p. 123).
As described in this publication, to access each of the memory elements of the MONOS type non-volatile semiconductor memory apparatus via signal lines (control lines) that are provided according to the number of the memory cells, not only two kinds of voltage values, but a plurality of kinds of voltage values need to be set for each of the signal lines (control lines).
In this case, devices that each have a pair of a charge pump circuit that operates with the power supply voltage and a regulator-may be prepared in the number of kinds of voltages required for each of the operations of the memory.
SUMMARY OF THE INVENTION
However, the devices that each have a pair of a charge pump circuit and a regulator need to be prepared in the number of required voltage values, such that, in particular, the area occupied in the chip by the charge pumps increases and the cost also increase. Also, the charge pump circuit consumes a relatively large amount of current. Therefore, as the number of required operation voltages increases, the number of devices that each have a pair of a charge pump circuit and a regulator need to be increased, and therefore there is a problem in that the current consumption for the entire apparatus increases.
The present invention addresses the problems described above, and provides a non-volatile semiconductor memory apparatus that lowers the area occupied by charge pump circuits and thus lowers the cost, and is capable of restricting current consumption by generating multiple kinds of voltage values by using one charge pump circuit even when many voltages values are required as operation voltages.
A non-volatile semiconductor memory apparatus in accordance with the present invention includes: a charge pump device that steps up a power supply voltage; one or a plurality of constant voltage devices that receive a voltage given from the charge pump, and respectively generate constant voltages having one or a plurality of voltage levels; and an operation voltage setting device that sets the one or the plurality of constant voltages that are respectively generated by the one or the plurality of constant voltage devices at a plurality of non-volatile memory elements to execute at least one of reading, programming and erasing operations for a specified non-volatile memory element within a memory array formed of the plurality of non-volatile memory elements.
With the structure described above, the power supply voltage is stepped up by the charge pump device. By using a voltage provided from the charge pump device, constant voltages having one or a plurality of voltage levels can be obtained by one or a plurality of constant voltage devices. In other words, constant voltages having a plurality of voltage values can be simultaneously generated by one charge pump device, and for example, voltage values generated by each of the constant voltage devices can be varied for each mode. The operation voltage setting device sets one or a plurality of constant voltages generated by one or a plurality of constant voltage devices for each of the non-volatile memory elements. As a result, even when the non-volatile memory element needs to be driven by a plurality of operation voltages, these multiple operation voltages can be obtained by one charge pump device. By providing only one charge pump device, the area occupied by the device can be reduced, and thus the cost can be reduced even when multiple operation voltages are needed, and also the current consumption can be restricted
The charge pump device steps up the power supply voltage to generate a plurality of voltages.
With this structure, the range of voltage values that can be generated by one or a plurality of constant voltage devices can be broadened.
Each of the one or the plurality of constant voltage devices is capable of generating constant voltages of different voltage values depending on read, program or erase mode for the non-volatile memory element.
With this structure, one or a plurality of constant voltage devices can obtain constant voltages according to an operation mode, i.e., a read mode, a program mode or an erase mode. Therefore, when a plurality of operation voltages are required for each of the modes, each mode can be executed.
The non-volatile memory element is a memory element that forms a twin memory cell controlled by one word gate and first and second control gates.
With this structure, for example, a reading operation, a programming operation or an erasing operation can be performed for the memory array with twin memory cells.
The operation voltage setting device sets voltage values provided from the one or the plurality of constant voltage devices independently for the first and second control gates, and an impurity layer to access trapped charge of the non-volatile memory element.
With this structure, the operation voltage setting device sets operation voltages required for a word gate that selects a twin memory cell, sets operation voltages required for the first and second control gates to select a non-volatile memory element within the selected twin memory cell, and sets required operation voltages for an impurity layer to access trapped charge of the selected non-volatile memory element. As a result, for example, a reading operation, a programming operation or an erasing operation can be performed for a specified non-volatile memory element in a specified twin memory cell.
The operation voltage setting device includes: a word line connected to a word gate of the twin memory cell in the same row; a control gate line that is commonly connected to the mutually adjacent first and second control gates in the same column of the twin memory cells arranged adjacent to each other in a row direction; and a bit line that is commonly connected to impurity layers to access trapped charge arranged in the same column of the mutually adjacent non-volatile memory elements of the twin memory cells arranged adjacent to each other in the row direction. Voltages provided from the constant voltage device are set independently for the control gate line and the bit line.
With this structure, the operation voltage setting device selects with the word line twin memory cells in the same row, commonly selects with the control gate line mutually adjacent first and second control gates in the same column of the twin memory cells arranged adjacent to each other in the row direction, a
Elms Richard
Luu Pho M.
Oliff & Berridg,e PLC
LandOfFree
Non-volatile semiconductor memory apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-volatile semiconductor memory apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile semiconductor memory apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3336639