Memory with shared bit lines

Details Memory with shared bit lines Memory with shared bit lines

2002-08-30

2004-08-10

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S051000, C365S063000, C365S190000

Reexamination Certificate

active

06775179

ABSTRACT:

This application claims priority of the earlier filing date, under 35 U.S.C. 119, of French Patent Application No. 01/11298, filed on Aug. 31, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to memories comprising a network of memory cell rows and columns and the associated memory cells.
2. Discussion of the Related Art
FIG. 1
schematically shows a cell of a static memory of random access type (SRAM) of conventional structure. The memory cell comprises inverters
1
,
2
, connected in antiparallel. The respective inputs of inverters
1
,
2
are connected to respective bit lines BL, {overscore (BL)} via switches
3
, controlled by a row selection signal conveyed by a word line WL. Each inverter
1
,
2
, is powered by a high voltage VDD and a low voltage GND, currently the ground.
To write an information in the memory cell, a voltage VDD is applied on one of bit lines BL or {overscore (BL)}, and a voltage GND is applied on the other one. Then, switches
3
are turned on to set the state of the inputs and outputs of inverters
1
and
2
. Switches
3
are then turned off and the state of the signals across inverters
1
and
2
is maintained.
To read an information from the memory cell, each bit lines BL and {overscore (BL)} is precharged to a voltage ranging between voltages VDD and GND, after which switches
3
are turned on so that the voltages on the bit lines vary according to the state of the signals across inverters
1
and
2
. A sense amplifier (not shown) connected to the bit lines provides a binary information in relation with the information kept in the memory cell.
Inverter
1
comprises a P-channel MOS transistor, PI
1
, in series with an N-channel MOS transistor, NI
1
. The source of transistor PI
1
is connected to voltage VDD and the source of transistor NI
1
is connected to voltage GND. The drains of transistors PI
1
and NI
1
are connected at a point O
2
. The gates of transistors PI
1
and NI
1
are also connected at a point O
1
.
Similarly, inverter
2
comprises transistors PI
2
and NI
2
connected like transistors PI
1
and NI
1
, the gates of transistors PI
2
and NI
2
being connected to terminal O
2
and the common drains of transistors PI
2
and NI
2
being connected to terminal O
1
. Switches
3
are formed of MOS transistors M
1
and M
2
, generally with an N channel.
FIG. 2
shows a portion of a conventional SRAM, each memory cell being represented by a reference block MCij. 8 cells have been shown, with i varying from 0 to 1 and j varying from 0 to 3. Conventionally, a single word line (WLi, i varying from 0 to 1) corresponds to a memory cell row and two bit lines (BLj and {overscore (BLj)}, j varying from 0 to 3) correspond to a memory cell column.
In such a memory, upon writing or reading of data into or from a memory cell, it is necessary to select, with one of word lines WL
0
, WL
1
, all the memory cells in the row where the searched memory cell is present. This results in a consumption which increases with the number of memory cells forming each row.
FIG. 3
shows a memory in which four word lines are associated with each row, each word line being connected to one memory cell out of four. Generally, if a memory comprises N word lines per row, the number of memory cells simultaneously selected by a word line will be divided by N. By reducing the number of memory cells selected upon each write and/or read operation, the memory consumption is decreased.
However, the increase in the number of word lines per row causes an increase in the memory surface area.
As an illustration,
FIG. 4
schematically shows an example of a topology of cell MC
01
of the memory of
FIG. 3
, in which the electric circuit of FIG.
1
and the additional word lines are formed in a technology with one polysilicon level and three metallization levels. Other polysilicon and metallization levels may be present and used.
The surfaces delimited by a thin line correspond to active areas of the semiconductor substrate or to polysilicon strips deposited on the substrate and corresponding to the gates of MOS transistors. Although the view is not drawn to scale, the relative dimensions and positions of each region are kept to show the real bulk of the integrated circuit. The double lines correspond to metal strips of level one. The horizontal thick black lines correspond to metal strips of level two, and the vertical thick black lines correspond to metal strips of level three. The crosses show contacts connecting, through the insulating layers located between the metallization levels and the polysilicon level, metal strips to active areas or to polysilicon strips or vias connecting, through the insulating layers located between the metallization levels, metal strips to other metal strips. For clarity, the metal strips are not shown with surface areas proportional to the surface areas of the active areas. However, the position of each line conforms to the real position of the corresponding metal strip in the integrated circuit.
In
FIG. 4
, the different elements shown in
FIG. 1
can be seen. The gate, source, and drain regions of the various transistors are designated with letter G, S, or D followed with the transistor reference.
Gates GM
1
and GM
2
of the respective MOS transistors M
1
and M
2
correspond to portions of polysilicon strip
10
. Active area
11
corresponds to MOS transistor M
1
, to MOS transistor NI
2
, and to the connection between these transistors. Similarly, active area
12
corresponds to MOS transistor M
2
, to MOS transistor NI
1
, and to the connection between these transistors. The respective gates GNI
2
and GPI
2
of MOS transistors NI
2
and PI
2
correspond to portions of polysilicon strip
13
. Similarly, the respective gates GNI
1
and GPI
1
of MOS transistors NI
1
and PI
1
correspond to portions of polysilicon strip
14
.
The different metal strips of level one, two, and three are used to connect the active areas and the polysilicon strips to obtain the equivalent electric diagram shown in FIG.
1
. In particular, the word line connected to gates GM
1
, GM
2
of transistors M
1
and M
2
is, in the present example, word line WL
01
corresponding to a horizontal metal strip of level two which is connected to polysilicon strip
10
via a vertical metal strip
17
of level one.
The topology of such a cell imposes for word lines WL
00
, WL
01
, WL
02
, and WL
03
to correspond to horizontal metal strips of level two, while word lines BL
1
and {overscore (BL
1
)} correspond to vertical metal strips of level three. To enable passing of the word lines, it is necessary to increase the surface area of each cell and thus the total surface area of the memory. In a manufacturing technology in which the smallest pattern has a length of 0.18 &mgr;m, a width &Dgr;x of 2.16 &mgr;m, a height &Dgr;y of 5.24 &mgr;m, and a surface area of 11.32 &mgr;m
2
are obtained for the memory cell of FIG.
4
. As a comparison, a memory cell of similar topology but with a single word line per row would have a width &Dgr;x of 2.16 &mgr;m, a height &Dgr;y of 3.6 &mgr;m, and a surface area of 7.78 &mgr;m
2
.
SUMMARY OF THE INVENTION
The present invention aims at providing an alternative memory architecture and associated memory cell topology.
The present invention aims at providing a memory having a surface area which does not vary when the number of word lines per row increases. In particular, the present invention aims at providing a memory, with several word lines per row, having a general surface area smaller than the surface area of an equivalent memory of conventional structure with a single word line per row or of the same order.
To achieve these objects, the present invention provides a memory block comprising a network of memory cell rows and columns, each memory cell being connected to a word line and two bit lines, in which at least two word lines are associated with each row, and at least two adjacent columns share the two bit lines, two memory cells of the two adjacent columns belonging to a same row bei

Affiliated with

Also associated with

Rating

Memory with shared bit lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory with shared bit lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory with shared bit lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3336169