Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-07-24
2004-08-17
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S109000
Reexamination Certificate
active
06777264
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and to the method for manufacturing the same.
FIG. 9
shows a schematic diagram of a conventional semiconductor device molded with resin.
FIG. 10
shows a top-view of the semiconductor device. These drawings show a Quad Flat Package (QFP).
This semiconductor device has a first semiconductor chip
91
, a second semiconductor chip
92
, a die pad
93
, a first adhesive layer
94
, a second adhesive layer
95
, electrodes
96
on the first semiconductor chip, electrodes
97
on the second semiconductor chip, inner leads
98
, metal wires
99
,
910
, a package portion
912
, outer leads
913
, and a pad support portion
914
. The semiconductor chips
91
and
92
are stacked on a die pad
93
.
The die pad
93
is lower than the inner leads
98
as shown in FIG.
9
and FIG.
10
. The hanging portion of the pad support portion
914
is bent, and the die pad and the inner leads are not at the same level. The bent portion is indicated by reference numeral
1011
in
FIG. 10
, this structure is called a downset. The thickness t1 of the resin on the semiconductor chip
92
is the same as the thickness t2 of the resin under the die pad
93
in the conventional design. The resin is filled proportionally during transfer molding because the thickness of resin on the semiconductor chip
92
and the thickness of resin under the die pad
93
are the same. Therefore, a short-circuit of wires on the semiconductor chip
91
and the semiconductor chip
92
is prevented. The warping of the package is also prevented.
The semiconductor chip
91
is fixed over the die pad
93
by the first adhesive layer
94
. The semiconductor chip
92
is fixed over the semiconductor chip
91
by the second adhesive layer
95
.
The electrodes
96
,
97
on each of the semiconductor chips are connected to inner leads
98
via metal wires
99
,
910
. For example, gold wires connect electrodes and inner leads. Some electrodes
97
on the semiconductor chip
92
are connected to the electrodes
96
on the semiconductor chip
91
. After the wire bonding, a resin (for example, epoxy resin) is molded on semiconductor chips. After the forming of the package portion
12
, the outer leads are plated with solder. The outer leads
913
are then transformed into a predetermined form.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device and the method for manufacturing the same that do not need a downset process. Therefore the yield is improved during the formation of a lead frame.
According to an embodiment of this invention, a semiconductor device comprises, a die pad having a top surface and a bottom surface, a first semiconductor chip having a top surface on which electrodes are formed and a bottom surface, and a second semiconductor chip having a top surface on which electrodes are formed and a bottom surface, the second semiconductor chip being smaller than the first semiconductor chip, wherein the top surface of the first semiconductor chip is fixed on the bottom surface of the die pad, the bottom surface of the second semiconductor chip is fixed on the top surface of the die pad.
A method for manufacturing the semiconductor device comprises forming a first adhesive layer on a bottom surface of a die pad, forming a second adhesive layer on a top surface of the die pad, fixing a top surface of a first semiconductor chip on the first adhesive layer, fixing a bottom surface of a second semiconductor chip which is smaller than the first semiconductor chip on the second adhesive layer.
REFERENCES:
patent: 5012323 (1991-04-01), Farnworth
patent: 5952725 (1999-09-01), Ball
patent: 6045886 (2000-04-01), Oka et al.
patent: 6072243 (2000-06-01), Nakanishi
patent: 6265760 (2001-07-01), Inaba et al.
patent: 6552437 (2003-04-01), Masuda et al.
patent: 6558791 (2003-05-01), Matsuura et al.
patent: 5-55452 (1983-03-01), None
patent: 05-109975 (1993-04-01), None
patent: 5-3284 (1993-08-01), None
Jr. Carl Whitehead
Oki Electric Industry Co. Ltd.
Vesperman William
Volentine & Francos, PLLC
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