Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-01-07
2004-02-03
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000, C714S769000
Reexamination Certificate
active
06687860
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a data transfer device and a data transfer method which are employed when data to be subjected to data processing using an array of a matrix format (rows and columns) are stored in or read from a RAM and, more particularly, to those suitable for the use of a paging RAM in data processing using an array having error correction codes in both the rows and the columns.
BACKGROUND OF THE INVENTION
When recording or transmitting data, for efficient recording or transmission, data are subjected to compression or coding according to a predetermined method, and the compressed or coded data are subjected to decompression or decoding which is the inverse of compression or coding, to be utilized. Further, in order to check and correct errors in data caused by noise or signal attenuation in reading, writing, or transmission of the data, predetermined codes for error checking and correction (hereinafter referred to as “error correcting codes”) are assigned according to a method such as parity bit, checksum, or cyclic redundancy check (CRC) when recording or transmitting the data, and error checking and correction (hereinafter referred to as “ECC”) using the error correcting codes is performed when decoding the data, whereby reliability is improved.
For example, there is a method in which data are arranged according to a format for error checking and correction having predetermined rows and columns, and row-direction parity data or column-direction parity data (error detecting codes) are assigned to every row or column.
In arithmetic operation to data such as ECC, a DRAM (Dynamic Random Access Memory), which has widely used in computer systems, is employed as a temporary storage means for working storage. A DRAM has addresses in both the row direction and the column direction, and data storage positions in the DRAM are specified by addressing. So, it is possible to realize a storage state suited to a format for error checking and correction, by successively storing data in the DRAM while specifying the storage positions.
Further, a paging DRAM in which data are processed in “page mode”, i.e., for each block having a fixed size and called “a page”, is employed for reducing the cycle time in memory access, i.e., the time interval between a memory access and next memory access, to achieve high-speed input/output of data to/from the memory. In this case, it is important for efficiency to frequently use the page mode when inputting/outputting data to/from the DRAM.
In a prior art decoder performing decoding with error correction, input data, which have been coded and are to be subjected to error correction, are temporarily stored in a buffer. As this buffer, an FIFO buffer according to FIFO (first-in first-out) is used. Then, the data stored in the FIFO buffer are fetched to be stored in a DRAM in a form suitable for an error correction array which is a format for error correction. Thereafter, the data stored in the DRAM are fetched to be subjected to ECC.
For example, in the case of using an error correction format having parity data in the column direction, when the data to be subjected to ECC are stored in the paging DRAM, the data are stored in the column direction according to the column-direction addresses of the DRAM. This storage enables data reading using the page mode in the column direction when the data stored in the DRAM are read for ECC, whereby high-speed memory access is achieved.
Also in a prior art encoder performing coding with error correction, similar processing is carried out. In the encoder, input data to be subjected to coding and error correction are temporarily stored in a buffer, and the data stored in the buffer are fetched to be stored in a DRAM in a form suitable for an error correction array which is a format for error correction. Then, the data so stored are subjected to coding with error correction, thereby generating coded data to which parity data for error correction are added.
For example, in the case of using an error correction format having parity data in the column direction, when the data to be subjected to ECC are stored in the paging DRAM, the data are stored in the column direction in accordance with the column-direction addresses of the DRAM. This storage enables data reading using the page mode in the column direction when the data stored in the DRAM are read for ECC coding, whereby high-speed memory access is achieved.
Further, in the prior art decoder, interpolation is carried out in the FIFO buffer to deal with the case where defects occur in the input data. For example, when using data sync bytes which are inserted in the input data at intervals of a predetermined amount of data, the data sync bytes are detected to check the amount of data between the data sync bytes included in the data stored in the FIFO buffer, and when the amount of data is less than a predetermined amount, dummy data is added to make the data between the data sync bytes have the predetermined amount.
In recent years, in order to improve the ECC precision, an error correction array of product codes, which is a format for assigning error correction codes to both rows and columns, has been used more frequently. When using this format, it is necessary to perform syndrome operation (polynomial operation) for both the row direction and the column direction in ECC, and the burden on the operation is considerable.
Furthermore, when performing error correction in a decoding process in a system having a control processor such as a computer system, this operation is repeated three times in the routine of “row-direction→column-direction→row-direction” or “column-direction→row direction→column direction”, to improve reliability of error correction. In this case, due to the increase in the frequency of access to the DRAM storing the data to be processed, high-speed access in the row direction (or the column direction) is required when the operation is carried out in the order of row-direction→column-direction→row-direction (or column-direction→row direction→column direction).
Moreover, when performing data processing in a computer system or the like, it is desirable to minimize the period during which a processor like a host CPU occupies a bus. Therefore, in a drive unit performing recording/reproduction of data in/from a data recording medium such as an optical disk, it is increasingly needed to increase the recording/reproduction speed, or the data transfer speed between the drive unit and a control unit such as a host computer. In such system, it is also desired to increase the error correction speed.
Consequently, in the data processing in this system, high-speed data input/output are strongly desired and, when using a paging DRAM, it is required that the page mode is used more frequently in both the row direction and the column direction to reduce the frequency of access to the DRAM.
In the prior art encoder or decoder, however, since the data stored in the FIFO buffer are fetched to be stored in the DRAM in the order as entered to the buffer, if the data are stored by using the page mode more frequently for one of the row direction and the column direction, the page mode cannot be frequently used for the other direction.
For example, in the case where the data have been sequentially input in the column direction of the correction array and then sequentially stored in the column direction of the DRAM, when the data are read in the column direction of the array to be subjected to error correction, the data can be successively read using the page mode. However, when the data are read in the row direction of the array, since the possibility that successive data are present in the same row is not very high, the page mode cannot be used frequently.
In the above-described ECC included in the decoding process, when the stored data are fetched in the order of row-direction→column-direction→row-direction and subjected to ECC, delays in the row-direction reading which has more access cycl
Iijima Yukio
Minakuchi Nobuaki
Nagai Takahiro
Okazaki Makoto
Ueda Yasushi
Chung Phung M.
Parkhurst & Wendel L.L.P.
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