Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2003-07-22
2004-11-30
Tran, M. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S230060
Reexamination Certificate
active
06826074
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a semiconductor integrated circuit including the semiconductor memory device. In particular, the present invention relates to a technology of effectively reducing leakage current of transistors in the case of using high-integration, high-density devices of a design rule in the generation of 0.13 &mgr;m gate length or later and operating at a power supply voltage as low as 1.2 V or less.
In general, to operate a semiconductor memory device at high speed even under low voltage, technologies using transistors having a low threshold voltage as its constituent transistors are adopted.
Use of a transistor having a low threshold voltage causes a problem that a large amount of OFF leakage current flows between the source and the drain of the transistor even during OFF periods. To solve this problem, conventionally, a negative voltage is set for word lines, and the source potential is shifted toward a positive potential, for example, to thereby effectively apply a negative bias to the transistor and thus limit the OFF leakage current to a small value.
Applying a large negative voltage to word lines and shifting the source voltage toward a positive potential are effective technologies producing no side effect when the device is sufficiently resistant to voltages. However, as the gate oxide film is thinned to below 2 nanometers with implementation of finer devices, a problem of gate leakage caused by a tunnel current arises. The conventionally proposed technology of driving word lines with a negative voltage and technology of offsetting source lines mentioned above increase the gate-source potential difference. Therefore, while succeeding in minimizing the OFF leakage current, these technologies disadvantageously cause a problem of increasing the gate leakage current.
With implementation of finer devices, the electric field between the gate and the drain of a transistor increases. This gives rise to a problem of gate-induced drain leakage (GIDL) current generated when a large potential difference is applied between the gate and the drain. The conventional technologies such as driving word lines with a negative voltage further induce this GIDL current, and thus have another problem of failing to minimize this new leakage current.
Leakage current from bit lines especially causes a problem. During data read operation, whether or not the potential of a precharged bit line has been drawn by a cell current is determined. Therefore, if there exists an amount of leakage current too large to be negligible with respect to the cell current, it is difficult to distinguish the cell current from the leakage current. As a result, it may take a long time before data read or erroneous data read may occur.
SUMMARY OF THE INVENTION
An object of the present invention is providing a semiconductor memory device capable of limiting gate leakage current and GIDL current to a small value while effectively limiting OFF leakage current.
To attain the object described above, in a semiconductor memory device of the present invention, the negative potential of non-selected word lines and the precharge potential of non-selected bit lines are appropriately set considering three types of leakage current, that is, OFF leakage current, gate leakage current and GIDL current. In addition, the potential of source lines of memory cells are appropriately set.
The semiconductor memory device of the present invention includes: a plurality of memory cells each drawing cell current according to data stored therein when selected; a plurality of word lines and a plurality of bit lines selected for accessing data in a specific memory cell among the plurality of memory cells; a power supply for providing a voltage corresponding to a high-level side potential of data in the plurality of memory cells; a word line potential supply source for supplying a potential to the plurality of word lines; and a precharge potential supply source for supplying a precharge potential to the plurality of bit lines, wherein a precharge potential supplied to non-selected bit lines among the plurality of bit lines by the precharge potential supply source is set at a value lower than the voltage of the power supply, a potential supplied to non-selected word lines among the plurality of word lines by the word line potential supply source is set at a predetermined negative value, and a total of the absolute value of the precharge potential of the non-selected bit lines supplied by the precharge potential supply source and the absolute value of the potential of the non-selected word lines supplied by the word line potential supply source is a value less than the voltage of the power supply.
In the semiconductor memory device described above, the precharge potential of the non-selected bit lines supplied by the precharge potential supply source may be set at a value less than half of the voltage of the power supply.
In the semiconductor memory device described above, a precharge potential supplied to a selected bit line among the plurality of bit lines by the precharge potential supply source may be set at a value higher than the precharge potential supplied to the non-selected bit lines by the precharge potential supply source and equal to or more than the half of the voltage of the power supply.
In the semiconductor memory device described, each of transistors constituting the plurality of memory cells may be constructed of a transistor in which the difference in current amount per unit gate width between OFF leakage current and gate leakage current is within two orders of magnitude.
In the semiconductor memory device described above, the voltage of the power supply may be 0.5 V to 1.2 V.
In the semiconductor memory device described above, the negative potential supplied to the non-selected word lines by the word line potential supply source may be changed depending on ambient temperature.
In the semiconductor memory device described above, the absolute value of the negative potential supplied to the non-selected word lines by the word line potential supply source may be larger when the ambient temperature is high than when it is normal.
Alternatively, the semiconductor memory device of the present invention includes: a plurality of memory cells each drawing cell current according to data stored therein when selected; a plurality of word lines and a plurality of bit lines selected for accessing data in a specific memory cell among the plurality of memory cells; a power supply for providing a voltage corresponding to a high-level side potential of data in the plurality of memory cells; a plurality of source lines for providing a low-level side potential of data in the plurality of memory cells; a word line potential supply source for supplying a potential to the plurality of word lines; a precharge potential supply source for supplying a precharge potential to the plurality of bit lines; and a source potential supply source for supplying a potential to the plurality of source lines, wherein a precharge potential supplied to non-selected bit lines among the plurality of bit lines by the precharge potential supply source is set at a value lower than the voltage of the power supply, a potential supplied to non-selected word lines among the plurality of word lines by the word line potential supply source is set at a predetermined negative value, a potential supplied to non-selected source lines among the plurality of source lines by the source potential supply source is set at a predetermined positive value, a total of the absolute value of the precharge potential of the non-selected bit lines supplied by the precharge potential supply source and the absolute value of the potential of the non-selected word lines supplied by the word line potential supply source is set at a value less than the voltage of the power supply, and the absolute value of the potential of the non-selected word lines supplied by the word line potential supply source and the absolute value of the
McDermott Will & Emery LLP
Tran M.
LandOfFree
Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3335821