Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2000-08-31
2004-06-22
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C712S217000, C712S219000, C712S245000, C712S248000, C712S026000, C711S125000, C711S214000, C711S216000
Reexamination Certificate
active
06754807
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to digital signal processors (DSPs) and, more specifically, to a method and apparatus for controlling vertical dependencies in a DSP.
BACKGROUND OF THE INVENTION
The availability of high-speed data communications is creating greater demand for ever-faster digital signal processors (DSPs). Digital signal processors are used in mobile phones, cordless phones, wireless personal digital assistant (PDA) devices, local area network (LAN) cards, cable modems, and a host of radio frequency (RF) communication devices, including conventional and high-definition television (HDTV) sets and radio receivers. A number of different approaches have been taken to decrease instruction execution time, thereby increasing DSP throughput.
Traditionally, digital signal processors have been designed to perform optimally on vector code (or array code). Because of this optimization, the performance of a conventional DSP suffers when running scalar code. Scalar code is a special case of vector code in which the array contains only a single element. Despite this drawback, emerging trends in the DSP marketplace indicate that scalar processing will become an increasingly important requirement for digital signal processors.
Managing vertical dependencies poses particular problems in a super-scalar DSP architecture having more than one instruction pipeline. For example, in a 2-way super-scalar architecture, instructions may be issued in order, but may be executed out-of-order in different pipes and the results may be written to the register files out-of-order. However, the instruction must be retired in order. A vertical dependency occurs whenever a first-issued or (previous) instruction generates a result that is stored in a target register and then used by a second issued (or subsequent) instruction. If the subsequent instruction is in a different pipeline (or way) than the previous instruction, it is possible that the subsequent instruction may be ready for execution before the previous instruction is completed. This may cause the subsequent instruction to read an older version of the result from the target register.
Scalar performance can be improved by using elaborate structures like renaming registers, completion buffers, and the like. The problems associated with managing vertical dependencies may also be addressed through the use of re-order buffers. For example, Intel P6 processors, high-end SPARC processors, and PowerPC processors use these structures and deliver impressive scalar performance.
Digital signal processors and apparatuses for handling vertical dependencies in digital signal processors are described in greater detail in U.S. Pat. No. 5,748,934 to Lesartre et al., U.S. Pat. No. 5,442,757 to McFarland et al., U.S. Pat. No. 5,550,988 to Sarangdhar et al., U.S. Pat. No. 5,560,032 to Nguyen et al., U.S. Pat. No. 5,606,670 to Abramsom et al., U.S. Pat. No. 5,625,789 to Hesson et al., U.S. Pat. No. 5,627,983 to Popescu et al, U.S. Pat. No. 5,627,985 to Fetterman et al., U.S. Pat. No. 5,630,157 to Dwyer, U.S. Pat. No. 5,644,753 to Ebrahim et al., U.S. Pat. No. 5,644,759 to Lucas et al. The teachings of the above-referenced patents are hereby incorporated by reference into the present disclosure as if fully set forth herein.
Unfortunately, the prior art circuits used to handle vertical dependency problems take up silicon area, increase design complexity, and consume power. Unfortunately, silicon area and power consumption are very important considerations in communication applications, such as mobile phones, and peripheral applications.
Therefore, there is a need in the art for improved digital signal processors that provide improved scalar performance. In particular, there is a need in the art for improved digital signal processors that provide improved management of vertical dependencies during scalar operations. More particularly, there is need for improved digital signal processors that are capable of efficiently handling vertical dependencies without using complex circuitry that occupies a large amount of circuit space and that consumes a large amount of power.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in a digital signal processor comprising a first instruction pipeline and a second instruction pipeline, an apparatus for managing vertical dependencies between instructions in the first and second instruction pipelines. To accomplish this, numerical identifiers (IDs) are assigned sequentially to the destination registers as they are dispatched to either of the first and second pipelines. Additionally, if an instruction about to enter a pipeline contains one dependent source operand that requires a result from a register (“the dependent source register”) that is dependent on execution of a prior instruction still in one of the pipelines, the ID of the dependent source register is assigned to the dependent source operand. If an instruction about to enter a pipeline contains two dependent source operands that require results from two dependent source registers, the ID of the dependent source register that is younger (i.e., most recently sent into pipelines) is assigned to the corresponding one of the two dependent source operands.
At the end of the instruction pipelines, the identifiers of executed (or retired) instructions are reclaimed. The present invention tracks a sequential list of retired IDs in order to determine the next sequential ID to be retired (referred to as “next retire ID”). A dispatched instruction from either pipeline is scheduled for execution by comparing the identifier associated with the source operands in the dispatched instruction with the next retire ID. If the dispatched instruction contains only one dependent source operand, the ID of the dependent source register is compared to next retire ID. If the dispatched instruction contains two dependent source operands, the previously determined younger ID assigned to one of the dependent source operands is compared to next retire ID. The dispatched instruction is scheduled for instruction only if the dependent source operand ID is less than of equal to the next retire ID.
In an exemplary embodiment, the first and second instruction pipelines comprise an instruction fetch stage, a decode stage, a dispatch stage, a schedule stage, an execution stage, and a retire stage. According to an advantageous embodiment of the present invention, the apparatus for managing vertical dependencies between instructions in the first and second instruction pipelines comprises: 1) identifier (ID) reclaim circuitry capable of determining a sequential set of retired identifiers associated with retired instructions executed by the first and second instruction pipelines, wherein the ID reclaim circuitry is further capable of determining a next retire ID sequentially following the sequentially set of retired identifiers; 2) first ID generation circuitry capable of sequentially assigning identifiers to destination registers associated with instructions entering the first and second instruction pipelines; 3) second ID generation circuitry associated with the first instruction pipeline capable of identifying a first dependent source register associated with a first dependent source operand of a first instruction entering the first instruction pipeline, and assigning an ID of the first dependent source register to the first dependent source operand; and 4) instruction scheduling circuitry capable of comparing the first dependent source operand ID of the first instruction with the next retire ID and scheduling the first instruction for execution if the first dependent source operand ID is one of: 1) less than the next retire ID and 2) equal to the next retire ID.
According to one embodiment of the present invention, the second ID generation circuitry is further capable of identifying a second dependent source register associated with a second dependent source oper
Driker Alexander
Parthasarathy Sivagnanam
Jorgenson Lisa K.
Munck William A.
Pan Daniel H.
STMicroelectronics Inc.
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