Active solid-state devices (e.g. – transistors – solid-state diode – Specified wide band gap semiconductor material other than... – Diamond or silicon carbide
Reexamination Certificate
2002-04-15
2004-06-15
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Specified wide band gap semiconductor material other than...
Diamond or silicon carbide
C257S037000, C257S132000, C257S136000, C257S154000, C257S162000, C257S264000, C257S266000, C438S040000
Reexamination Certificate
active
06750477
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an improvement in the structure of a static induction transistor.
2. Conventional Art
In association with a demand for increasing electric power and for a high frequency operation for a power inverter, semiconductor switching elements with a low loss and a high speed operation as well as with a large controllable current are desired.
To meet with these demands, a switching element using silicon carbide (SiC) as its base material is proposed. For example, a power MOSFET as disclosed In “High-Voltage Double-Implanted Power MOSFETs in 6H-SiC” (IEEE Electron Devices Letters, Vol. 18, NO.3, p.93-95(1997)) is investigated. However. in the power MOSFET in which an inversion layer having a low carrier mobility is used for a channel layer serving as a current passage, there arises a problem of increasing its on voltage.
Another static induction transistor is promising which does not use such inversion layer as a channel layer in order to avoid such problem as disclosed, for example in “Field-effect Transistor Versus Analog Transistor (State Induction Transistor)” (IEEE Trans. on Electron Devices, Vol. ED-22, p.185-197, 1975).
FIG. 2
shows a perspective cross sectional view of a conventional static induction transistor. A semiconductor substrate
1
of the static induction transistor is constituted by an n
+
conductivity type region
2
, an n
+
conductivity type region
3
, a p
+
conductivity type region
4
and n
+
conductivity type source layer
5
, and is provided with a source electrode
6
, a drain electrode
7
and a gate electrode
8
. Through reducing the potential of the gate electrode
8
with respect to the source electrode
6
, a depletion layer is spread between the p
+
conductivity type layers
4
, namely, in a so-called channel region, thereby a current flowing between the drain electrode
7
and the source electrode
6
can be turned off. For example, in a published abstract entitled, “Electrical Characteristics of A Novel Gate Structure 4H-SiC Power Static Induction Transistor” (International Conference on Silicon Carbide, III—nitrides and Related Materials-1997, Abstract p.443, (1997)), there was reported a possibility of realizing an extremely low on resistance through use of an SiC base material for the channel region.
However, with the base structure as shown in
FIG. 2
, there arises a problem that its off characteristic is extremely undesirable because of a production process limitation inherent to SiC, which will be explained below. Namely, in the above conventional static Induction transistor, it is necessary to narrow the gap between the p
+
conductivity type layers
4
to such an extent that the respective depletion layers thereof overlap each other, when a gate voltage is applied thereto during off period thereof, as well as the p
+
conductivity type layers
4
have to be formed as deep as possible and in a high density layers so as to hold an off ability with a comparatively low gate voltage for a high reverse voltage of hundreds to thousands volt However, the junction of SiC is designed to make use of its inherent material characteristic that the dielectric breakdown electric field of its junction is about ten times larger than that of Si, the impurity density of the n
+
conductivity type layer
3
is usually set in a high density of 70-100 times in comparison with the use of Si. Therefore, the expansion of the depletion layers is extremely limited. For this reason it is necessary that the gap between the p
+
conductivity type layers
4
has to set at an extremely narrow amount such as about 1 &mgr;m or less than 1 &mgr;m in order to obtain a pinch off effect due to the depletion layer. Further, a deep p conductivity type layer is formed for Si through a thermal diffusion of acceptor impurities such as boron and aluminum. However, since the diffusion coefficients of these impurities are extremely low for SiC, the thermal diffusion method can not be used for SiC and the deep p conductivity type layer has to be directly formed only by an ion implantation method. However, it is quite difficult to selectively form a deep implantation layer of about 1 &mgr;m with narrow gaps only through an ion implantation. This is because it is quite difficult to produce an implantation mask with a large film thickness and a narrow gap. For example, when using a photo resist which is commonly and usually used as an implantation mask, an implantation energy of about 500 keV is required for implanting boron in a depth of 1 &mgr;m, and the mask thickness of more than 4 &mgr;m is necessary for enduring the implantation energy. It is very hard to process the width and gap in such a thick photo resist in a range of less than 1 &mgr;m with a high accuracy. Accordingly, with the static induction transistor (hereinafter, abbreviated as SIT) using SiC and with the base structure as shown in
FIG. 2
, a characteristic with a large gate off gain can not be expected. Moreover, a realization of an SIT with a normally off function is almost impossible.
As has been explained above, when applying the conventional measures used in connection with Si in manufacture of a static induction transistor using SiC as its base material, a necessary channel width is about 1 &mgr;m for obtaining a comparatively high off gain. Therefore, the formation of a deep p conductivity type gate layer with a high impurity density through an ion implantation method is quite difficult due to the limitation of the implantation mask processing accuracy. Further, since the source layer has to be formed in such a narrow gap, an extremely high accuracy is required for their pattern matching. As a result, a production of an SIT having an excellent off characteristic including normally off function is difficult.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a static induction transistor with a new structure which resolves the above mentioned problems.
Another object of the present invention is to provide a static induction transistor with a new structure which shows an excellent off characteristic.
Still another object of the present invention is to provide a static induction transistor with a new structure which permits a production thereof with a high yield.
In order to achieve the above objects, a gate region of the static induction transistor according to the present invention is structured in such a manner to provide a first gate layer and a plurality of second gate layers which are surrounded by the first gate layer and of which depth, width and gap are smaller than those of the first gate layer.
With the above measure, when the static induction transistor moves from an on state to an off state, the following occurs. At first an electron flow from a source layer is prevented with a low gate voltage due to a pinch off effect in other words there is overlapping of depletion layers of the second gate layers having a narrow width. Thereafter, an increasing drain voltage is prevented up to a high voltage with a further high gate voltage due to a pinch off effect, in other words, there is overlapping of depletion layers of the first gate layer having a wide width, and thereby an SIT with an excellent off characteristic is realized. Herein, when the gap between the second gate layers is extremely narrowed, an SIT having a normally off function can be realized which exerts a pinch off effect under a short circuited or an open circuited condition between a gate electrode and a source electrode.
Further, according to the present invention, when forming the second gate layers with a narrow width through an ion implantation, an extremely thin implantation mask can be applied depending on a decrease of the implantation energy and an implantation mask permitting a high processing accuracy is obtained. As a result, an SIT with a high off gain can be produced with a high yield.
REFERENCES:
patent: 5143859 (1992-09-01), Harada
patent: 5323029 (1994-06-01), Nishizawa
Ohno Toshiyuki
Oikawa Saburo
Onose Hidekatsu
Yatsuo Tsutomu
Antonelli Terry Stout & Kraus LLP
Ho Hoai
Tran Mai-Huong
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