Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-07-15
2004-06-29
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06757876
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to microelectronic chip design, and more particularly to a method of modeling a logic cell for circuit level models.
2. Description of the Related Art
Generally, integrated circuits are electrical circuits comprised of transistors, resistors, capacitors, and other electrical components on a single semiconductor chip in which the components are interconnected to perform a given function. A circuit designer designs an integrated circuit by creating a circuit schematic indicating the electrical components and their corresponding interconnections. Moreover, designs are simulated by computer-aided design programs to verify the functionality and to ensure that performance goals are satisfied.
The layout of an integrated circuit contains parasitic resistances and capacitances from the interconnections and devices. The values of these so-called parasitics are functions of the process parameters, shape and dimensions of a particular geometry, and relationship of a particular geometry to other geometries. These parasitics affect the performance and possibly the functionality of an integrated circuit. Consequently, during the design phase of an integrated circuit, these parasitics are extracted from a layout and taken into consideration during circuit simulation.
Integrated circuits which are fabricated using deep sub-micron processes are becoming mainstream, but are complex. One of the challenges faced by today's deep sub-micron integrated circuit designers is the issue of parasitic effects of passive interconnect ions. Deep sub-micron integrated circuit designers are recognizing that these effects cannot be ignored, otherwise the design can fail. These effects also play an important role in timing, power, reliability, as well as noise performance. In order to take parasitic effects of passive interconnects into consideration in post layout analysis for timing, power, etc., it is necessary to create electrical models for the physical connections present between the various devices in a deep sub-micron integrated circuit design, a process known as parasitic extraction. As such, multiple parasitic extractions performed repeatedly at different points in time to create multiple electrical models for different views of the design are often required.
General designs are created using hierarchical methodologies. Here, small circuits are designed and evaluated, and then connected to larger functions until the full chip is assembled. Each element of the hierarchy is called a cell (logic cell) and the basic circuit functions, which include devices and interconnects, are called leaf-cells.
The problem associated with most conventional extraction programs is that they work in a flat manner. That is, the conventional extraction programs ignore the design hierarchy. Some packages have the option to use design hierarchy without a check and simply ignore placement dependent changes. These conventional systems make the user responsible for the inaccuracies.
More sophisticated solutions use an active radius around each wire and check whether the environment within this radius is constant. Variations outside of this radius are considered small and ignored. However, because these solutions are often rigid in their application, this leaves open the possibility that some variations important in the hierarchical design are ignored, thus resulting in an inaccurate manner in which to model a logic cell. Therefore, there remains a need for a new and improved process and system of modeling a logic cell using parasitic extraction techniques in a worst-case environment for the logic cell.
BRIEF SUMMARY OF THE INVENTION
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional modeling techniques for logic cells using hierarchical extraction processes, the present invention has been devised, and it is an object of the present invention to provide a system and method for modeling a logic cell.
In order to attain the object suggested above, there is provided, according to one aspect of the invention, a method of extracting circuit characteristics from a circuit design that extracts first cell characteristics from a portion of the circuit design using a first set of environmental conditions. Next, the invention extracts second cell characteristics from the portion of the circuit design using a different, second set of environmental conditions. The invention determines the difference between the first cell characteristics and the second cell characteristics. The invention compares this difference to a predetermined standard. The invention labels the portion of the circuit design as freely placeable within any area of said circuit design if the difference is less than the predetermined standard. Next, the invention replaces the portion of the circuit with a placeholder cell if the portion of the circuit design is freely placeable. The invention forms the placeholder cell in a process that includes shorting all conductors in the portion of the circuit design to a ground node. The invention then merges all the conductors in a given level of the portion of the circuit design. Next, the invention removes all the conductors that are covered by overlying conductors from the portion of the circuit design. The invention merges the conductors outside the portion of the circuit design that are within a predetermined distance to the circuit design to conductors within the portion of the circuit design. The circuit characteristics comprise at least one of capacitance, impedance, power, and resistance.
The first environmental conditions represent the best environment and the second environmental conditions represent the worst environment. The best environment has the minimum amount of wiring adjacent the portion of the circuit and the worst environment has the maximum amount of wiring adjacent the portion of the circuit. The invention calculates average cell characteristics from the portion of the circuit design for the placeholder cell.
To decouple the full (schematic and parasitic) model of one cell from its environment both the impact of the environment on the cell and the impact of the cell on the environment must be considered. Generally, according to the present invention, the amount of variation a cell can tolerate must be determined. Then, a calculation of how much variation different placements can cause is performed. A decision of whether the cell is freely placeable is made based on the level of variation for that cell.
Designed blocks of circuitry or cells are preferably reused in different environments, with different wires running over, next to, or even through the previously characterized design. If all these different environments do not change the characteristic of the description of this cell significantly, the cell can be placed anywhere on the die without timing model changes, and it is considered freely placeable. When the cell is found to be freely placeable the cell undergoes parasitic extraction in an “average” environment (centered between the worst and best environment standards) and the timing model for the cell is created. The model can be stored for use with the final assembly of the part with all leaf cells and interconnect cells, or it can be characterized and simplified, when a final detailed assembly is not required. The next step the invention takes is characterization of the parent cell without the just characterized cell being present. For this step the invention replaces the cell with a simplified model leaf cell, which just contains the important elements for characterization of the interconnect cell. This leaf cell model is sometimes called a placeholder. This highly simplified placeholder design contains just the features which can impact the extraction of the interconnect, or more generally the environment of the leaf cell, so that internal extraction calculations internal to the leaf cell itself can be dropped out of further extraction processes. This placeho
Kotulak, Esq. Richard M.
Levin Naum
McGinn & Gibb PLLC
Siek Vuthe
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