Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-16
2004-02-03
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S395000
Reexamination Certificate
active
06686623
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the configuration of a nonvolatile memory formed by using a semiconductor. In particular, the invention is effective for nonvolatile memory in which the channel length is 2 &mgr;m or less or even 0.5 &mgr;m or less.
2. Description of the Related Art
The IC memories that perform data storage and holding in computers are generally classified into the RAM and the ROM. Examples of the RAM (random access memory) are the DRAM (dynamic RAM) and the SRAM (static RAM). If the power is turned off, data stored in the DRAM or the SRAM are lost.
On the other hand, examples of the ROM (read-only memory) are the mask ROM and the PROM (programmable ROM). The mask ROM and the PROM have an advantage that even if the power is turned off, data stored there are not lost. The PROM is classified into the EPROM (erasable PROM) in which data erasure is performed by using ultraviolet light, the EEPROM (electrically erasable PROM) in which data erasure is performed electrically, the flash memory (flash EEPROM) in which data erasure is performed en bloc electrically, and other types.
To fully utilize their marked advantage of permanent data holding, studies and developments on nonvolatile memories have been made energetically. At present, the possibility of using nonvolatile memories instead of magnetic memories is being discussed.
As for such IC memories, it is necessary to not only improve the reliability and performance but also increase the storage capacity. That is, as in the case of other types of ICs, such memory ICs are being developed according to the scaling law while miniaturization techniques are always adopted.
However, since basically nonvolatile memories store data according to the same principle of operation as field-effect transistors (hereinafter referred to as FETs), the short channel effect, which is known as causing serious problems in the FET operation, also causes serious problems in the operation of nonvolatile memories as the miniaturization advances.
In particular, the phenomenon called “punch-through” decreases the source-drain breakdown voltage and hence makes the current control with the gate electrode difficult. A SSW-DSA structure (Nikkei Microdevices, pp. 47-48, May issue, 1992) is a conventional example of increasing the punch-through resistance.
In the field of the FET, the SSW-DSA structure is a structure that utilizes a technique called a pocket structure in which an impurity region having the same conductivity type as the substrate is provided in the channel-drain junction portion. This structure can prevent the occurrence of a punch-through phenomenon by suppressing the expansion of the drain depletion layer.
However, in nonvolatile memories, electron-hole pairs are generated by positively causing impact ionization in the channel-drain junction portion. Therefore, a large amount of holes flow to the substrate side as electrons are injected into the floating gate.
However, in the SSW-DSA structure, a large amount of holes thus generated act in no other way than flow into the substrate terminal. This may cause a problem that a parasitic source-substrate-drain bipolar is formed to cause a kink phenomenon (an abnormal increase in drain current).
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problems, and an object of the invention is therefore to realize a high-performance memory by effectively preventing or weakening the short channel effect that occurs in miniaturizing nonvolatile memories.
According to a first aspect of the invention, there is provided a nonvolatile memory comprising a source region, a drain region, and an active region that are formed by using a single crystal semiconductor; impurity regions provided locally in the active region; and an intrinsic or substantially intrinsic channel forming region interposed between the impurity regions.
According to a second aspect of the invention, there is provided a nonvolatile memory comprising a substrate having an insulating surface; a source region, a drain region, and an active region that are formed over the substrate by using a semiconductor thin film that is a single crystal or is substantially regarded as a single crystal; impurity regions provided locally in the active region; and an intrinsic or substantially intrinsic channel forming region interposed between the impurity regions.
According to a third aspect of the invention, there is provided a nonvolatile memory comprising a source region, a drain region, and an active region that are formed by using a single crystal semiconductor; impurity regions provided locally in the active region by adding an impurity element that is a group-13 or group-15 element; and an intrinsic or substantially intrinsic channel forming region interposed between the impurity regions.
According to a fourth aspect of the invention, there is provided a nonvolatile memory comprising a source region, a drain region, and an active region that are formed by using a single crystal semiconductor; impurity regions provided locally in the active region by adding an impurity element that is a group-13 or group-15 element, the impurity regions serving to prevent a depletion layer from expanding from the drain region toward the source region; and an intrinsic or substantially intrinsic channel forming region interposed between the impurity regions.
According to a fifth aspect of the invention, there is provided a nonvolatile memory comprising a substrate having an insulating surface; a source region, a drain region, and an active region that are formed over the substrate by using a semiconductor thin film that is a single crystal or is substantially regarded as a single crystal; impurity regions provided locally in the active region by adding an impurity element that is a group-13 or group-15 element; and an intrinsic or substantially intrinsic channel forming region interposed between the impurity regions.
According to a sixth aspect of the invention, there is provided a nonvolatile memory comprising a substrate having an insulating surface; a source region, a drain region, and an active region that are formed over the substrate by using a semiconductor thin film that is a single crystal or is substantially regarded as a single crystal; impurity regions provided locally in the active region by adding an impurity element that is a group-13 or group-15 element, the impurity regions serving to prevent a depletion layer from expanding from the drain region toward the source region; and an intrinsic or substantially intrinsic channel forming region interposed between the impurity regions.
In the above nonvolatile memories, it is preferable that the impurity regions be provided in striped form so as to reach both of the source region and the drain region.
In the above nonvolatile memories, it is preferable that an impurity element contained in the impurity regions have a concentration that is 1×10
17
to 5×10
20
atoms/cm
3
.
In the above nonvolatile memories, it is preferable that the substrate be a crystallized glass substrate provided with an insulating film on a surface thereof.
It is effective to use any of the above nonvolatile memories as a recording medium.
The main feature of the invention is that impurity regions are formed locally in the active region and the impurity regions prevent a depletion layer from expanding from the drain region toward the source region. In this specification, a region that is enclosed by a source region, a drain region, and field oxide films is called in active region and the active region is divided into striped impurity regions and channel forming regions.
Since the effect of preventing expansion of a depletion layer looks like pinning the depletion layer, the inventors define the term “pinning” as meaning “prevention” (or “suppression”).
REFERENCES:
patent: 4454524 (1984-06-01), Spence
patent: 4495693 (1985-01-01), Iwahashi et al.
patent: 4549336 (1985-10-01), Sheppard
patent: 4697198 (1987-09-01), Komori et al.
paten
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Crane Sara
Semiconductor Energy Laboratory Co,. Ltd.
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