Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-10-15
2004-08-24
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S637000, C438S700000
Reexamination Certificate
active
06780740
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacture and specifically to a method for fabricating a semiconductor memory device. More specifically, this invention relates to a method for fabricating a floating gate semiconductor device such as an electrically erasable programmable read only memory device (EEPROM).
BACKGROUND OF THE INVENTION
One type of memory device is known as a programmable read only memory (PROM). This is a nonvolatile memory which maintains the stored data even through periods of no power. In some applications however, it is advantageous to change the instructions or data in a PROM. This requires that the data within the device be erased and the device be electrically reprogrammed with other data. With a UV-EPROM, erasure is accomplished by exposure to UV light for a prolonged time period.
Because it is relatively expensive to reprogram devices using UV light, electrically erasable programmable read only memory devices (EEPROM) have been developed. These devices are also known as flash EEPROMs because the data within the device can be erased using an electrical erase signal. The term flash is used because an array of memory cells can be erased much faster than with a UV-EPROM (e.g., 1 second vs. 20 minutes). Typically, a flash EEPROM includes a control gate and a floating gate which control current flow through a channel region of a MOSFET.
FIG. 1
illustrates a memory array
10
that includes one type of prior art flash EEPROM cell
12
. A silicon substrate
14
includes a field oxide (FOX)
16
for isolating active areas
18
formed on the substrate
14
. Each EEPROM cell
12
comprises a conventional FET having a source, a drain and a gate region. For simplicity, all of the elements of the EEPROM cells
12
are not shown. However, each EEPROM cell
12
includes a floating gate
20
formed over a gate oxide
24
. A control gate
22
forms the word line of the array
10
and is separated from the floating gates
20
by an insulating layer
26
. Typically the insulating layer
26
is an oxide
itride/oxide (ONO) composite film. The floating gate
20
and control gate
22
are typically formed of doped polysilicon.
In operation of the flash EEPROM cell
12
, the presence of electrons in the floating gate
20
alters the normal operation of the FET and the flow of electrons between the source and drain of the FET. Programming of the flash EEPROM cell
12
can be accomplished by hot-electron injection into the floating gate
20
. The erasing mechanism of the flash EEPROM cell
12
is electron tunneling off the floating gate
20
to the drain region of the FET.
One problem with constructing a prior art memory array
10
in this manner is in forming the floating gates
20
. Typically, the floating gates
20
are defined by blanket depositing a layer of polysilicon and then etching the layer in a required pattern with spaces
28
between adjacent EEPROM cells
12
. A photolithographic process can be used to etch the floating gates
20
. This photolithographic process requires a critical mask formation and alignment step. In order to insure adequate alignment during this step, the floating gates
20
are typically made larger than is necessary. In other words the floating gates
20
must extend over the full thickness of the FOX
16
on either side of the active areas
18
of the array
10
. A pitch of the floating gates
20
and the cells
12
is thus increased by the critical mask formation. Furthermore, using this method of formation the floating gates
20
must be made thicker than is necessary to provide a proportional capacitive coupling of the floating gates
20
relative to the control gates
22
.
In view of the foregoing, it is an object of the present invention to provide an improved method for forming floating gate MOSFET devices such as flash EEPROMs. It is a further object of the present invention to provide an improved floating gate MOSFET device and an improved flash EEPROM. It is yet another object of the present invention to provide an improved method for forming a floating gate of a semiconductor device in which the floating gate is self aligned and a critical masking step for forming the floating gate is eliminated. It is yet another object of the present invention to provide an improved method for forming a floating gate MOSFET device, such as a flash EEPROM, using chemical mechanical planarization.
Other objects, advantages and capabilities of the present invention will become more apparent as the description proceeds.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved method for forming a floating gate semiconductor device is provided. The method uses a chemical mechanical planarization (CMP) step to form the floating gate in a location that is self aligned to a gate area of the device.
The method includes forming an active area on a silicon substrate and a gate oxide in the active area. An isolation layer, comprising a field oxide, or other insulating material, is also formed on the substrate in a pattern which forms a recess having sidewalls which surround and enclose the active area. A conductive material is then deposited over the isolation layer, over the sidewalls of the recess, and onto the gate oxide. During the CMP process the conductive material is planarized to a planar endpoint defined by a surface of the isolation layer. In other words, all of the conductive material except for the material within the recess is removed. This remaining material is self aligned with the gate area and forms the floating gate.
In an illustrative embodiment, a flash EEPROM is formed. The flash EEPROM includes a field effect transistor (FET) comprising a source, a drain and a gate oxide. The FET is formed in an active area of the substrate isolated from adjacent active areas within an enclosed recess formed by a field oxide. The flash EEPROM also includes a floating gate formed by depositing a conductive layer (e.g., polysilicon) over the gate oxide and field oxide and then chemically mechanically planarizing the conductive layer to an endpoint of the field oxide. This forms the floating gate in alignment with the gate area of the FET without the requirement of a critical masking step. Following the formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer. The control gate also serves as the word line for the device.
In an alternate embodiment of the invention, rather than planarizing the floating gate to an endpoint of the field oxide, the conductive material for the floating gate is initially deposited to a thickness that is less than a depth of the recess formed in the field oxide. This forms the surface of the conductive material in a concave shape which increases an interface area of the floating gate and the control gate and the capacitive coupling between these elements. The capacitive coupling can also be increased by forming the floating gate with a rough surface having an increased surface area. This can be accomplished by forming the floating gate out of a hemispherical grain (HSG) polysilicon.
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Doan Trung Tri
Lowrey Tyler A.
Gratton Stephen A.
Micro)n Technology, Inc.
Nhu David
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