Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2002-11-20
2004-11-09
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S697000, C438S693000
Reexamination Certificate
active
06815357
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing apparatus of a wiring substrate and a manufacturing process for a wiring substrate using the apparatus, and particularly, to a polishing and manufacturing apparatus and a process for selectively forming a wiring substrate consisting of a copper or copper-based alloy (hereinafter referred to as “Cu”) and a diffusion preventing layer (“barrier layer”) for Cu.
2. Description of the Related Art
In recent years, replacement of interconnects using an aluminum alloy (which will hereinafter be abbreviated as “Al”) with Cu interconnects has started in order to satisfy the requirement for speeding-up of large-scale semiconductor integrated circuits (abbreviated as “LSI”). Cu interconnects are usually, formed by the damascene method. In this method, as described in JP-A No. 278822/1990, a hole or trench (hereinafter referred to collectively as a “trench”) is made in advance in an insulating film; a thin barrier layer made of tantalum (Ta) or tantalum nitride (TaN) for preventing Cu diffusion and improving adhesion is formed in the trench; a Cu layer is formed to embed the trench therewith; and the Cu layer and barrier layer at portions other than the trench are removed by chemical mechanical polishing (hereinafter referred to as CMP or “polishing”), whereby a damascene Cu interconnect structure having the Cu layer and the barrier layer embedded only in the trench is formed.
After completion of polishing, however, Cu embedded in the insulating film is exposed directly from the surface of the polished wiring substrate. Although multilevel interconnection by using Cu requires formation of an insulating film over Cu, a silicon oxide (“SiO
2
”) film or many insulating films composed of other materials are not suited, because they are poor in adhesion with Cu and moreover, prompt diffusion of Cu occurs in such insulating films. There are not many insulating materials which can be formed directly on the Cu exposed surface of a wiring substrate, have adequate adhesion and suppress Cu diffusion. Currently, silicon nitride (“SiN”), silicon carbide (“SiC”) and the like are employed. They are however deficient in diffusion preventive capability and adhesion with Cu. Moreover, these materials have a high dielectric constant so that use of them increases electrostatic capacity between interconnects, thereby increasing the propagation delay of interconnect signals. In recent years, use of low-dielectric-constant materials as an insulating film for forming a trench therein has been studied in order to reduce electrostatic capacity between interconnects. The low-dielectric-constant material is usually low in density and diffusion rate of Cu therein is larger than in an SiO
2
film. So, there is a high risk that a further deterioration in long-term reliability occurs in the Cu multilevel interconnection using a low-dielectric-constant material. The conventional method of covering a Cu polished surface with an insulating film made of a silicon compound restricts the ability to improve the wiring characteristics and prevents maintenance of sufficient long-term reliability.
As another countermeasure against the above-described problem, a method of forming a cobalt (Co)—tungsten (W) alloy (“Co—W alloy”) selectively on the Cu polished surface by electroless plating is described in “Proceedings of the Second International Symposium on Low and High Dielectric Constant Materials: Materials Science Processing and Reliability Issues (published by The Electrochemical Society), Vol. 97-8, 186-195”. As illustrated in
FIG. 3A
, the wiring substrate
30
comprises a first insulating film
301
formed on a substrate
300
made of, for example, silicon, and after making an interconnect trench in the insulating film, a first barrier layer
303
and a first Cu interconnect layer
304
are embedded in the trench in order to improve adhesion with Cu and prevent diffusion of Cu. Polishing is usually employed for leaving the first Cu layer
304
and first barrier layer
303
only in the trench. By selective electroless plating, a barrier metal layer
305
is selectively formed over the Cu surface as illustrated in
FIG. 3B
(such a barrier metal layer formed by electroless plating will hereinafter be called “plated barrier layer”). Cobalt (Co) and nickel (Ni) are known materials of the plated barrier layer
305
. In the electroless plating, an oxide on the surface of the underlying metal layer, for example, the first Cu interconnect layer
304
is etched or reduced, and depending on a slight difference in the chemical condition between the Cu surface and the peripheral surface of the first insulating film, particles for the formation of the plated barrier layer are precipitated only on the surface of the metal layer. Moreover, even within the surface of the Cu interconnect
304
, precipitation of particles, which will constitute the plated barrier film
305
, tends to occur easily at portions different in the state from the periphery, for example, so-called defective portions such as grain boundary or scratches generated during polishing. These precipitated particles are connected each other as illustrated in
FIG. 3B
, thereby forming a continuous plated barrier film
305
having a diffusion preventive capability against the Cu interconnect
304
. To impart the plated barrier film
305
with sufficient Cu diffusion barrier effect, it was conventionally necessary to form the film having a thickness of 0.1 micron or greater. Such thickness of the plated barrier film
305
is too large where the Cu interconnect has the minimum processing dimension of about 0.2 micron or less. Only a slight difference exists in the chemical condition between the surface of the Cu interconnect
304
and the surface of the first insulating film
301
at the periphery thereof. If some pollutants or scratches exist on the surface of the first insulating film
301
, abnormal growth particles
305
b
inevitably occur even at such defective portions. The conventional electroless plating therefore involves another problem that with the growth of the plated barrier film
305
as thick as 0.1 micron, the abnormal growth particles
305
b
increases, causing a short-circuits between interconnects and/or lower yields.
The conventional electroless plating is conducted in a manner as illustrated in
FIG. 4. A
plating vessel
43
stored in a heating tank
40
is filled with a plating solution
45
for a plated barrier layer. The solution is kept at a predetermined temperature by the heating tank
40
. Electroless plating is usually conducted at 70 to 90° C. The plating solution
45
is stirred by a stirring rod
44
. A wiring substrate
46
which has been surface-treated in advance is immersed in the solution for forming a barrier layer by plating. Since the temperature of the plating solution
45
is high, evaporation and, in turn, a change in the composition of the solution tend to occur. In order to prevent them, hollow plastic balls
47
are floated all over the surface of the plating solution. In such a conventional electroless plating method, the above-described surface treatment is conducted as pre-treatment for the formation of a plated barrier layer selectively on the Cu surface. The effect of this pre-treatment for improving selectivity, however, depends only on the effect of chemical treatment of the wiring substrate
46
with an acid or alkali solution. Effects of this pretreatment for removing foreign matters adhered to the substrate or pollutants whose removal is not intended by the chemical solution are not sufficient and abnormal nuclear growth of the plated barrier layer on the first insulating film cannot be prevented fully. On the contrary, sufficient removal of the substances adhered to the Cu surface sometimes makes it difficult to allow particles to grow all over the metal surface.
In JP-A No. 22285/1998, proposed is an idea of simultaneously causing polishing and plating of the polished surface by adding components of a plating solution
Akahoshi Haruo
Hom-ma Yoshio
Itabashi Takeyuki
Nakano Hiroshi
Sakuma Noriyuki
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Picardat Kevin M.
Reed Smith LLP
Renesas Technology Corporation
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