Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-18
2004-02-24
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S316000, C257S319000, C257S320000, C257S321000, C438S263000, C438S264000, C365S185010
Reexamination Certificate
active
06696724
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device comprising a non-volatile memory cell for storing at least one bit, according to the preamble of claim
1
.
BACKGROUND AND SUMMARY OF THE INVENTION
Such non-volatile memory cells are well known from the prior art in a plurality of varieties.
FIG. 1
shows schematically a cross-section of an exemplary prior art planar 2T non-volatile memory cell.
The depicted 2T non-volatile memory cell
1
, also known as Flash cell, is of the planar type and comprises two distinct transistors, viz. a floating gate transistor FT and an access transistor AT. On a p-type substrate
2
, an n-type drain region
3
, an n-type source region
4
, an n-type doped region
5
are formed. On the surface, between drain region
3
and doped region
5
, a floating gate
6
is formed on a thin gate oxide
7
. On top of the floating gate
6
, a control gate
8
is formed. The control gate
8
is separated from the floating gate
6
by an isolating layer
14
, e.g., an oxide layer or an oxide-nitride-oxide layer. Insulating side spacers
9
are formed on the sides of the stack of the floating gate
6
and the control gate
8
. Adjacent to this stack, between the doped region
5
and the source region
4
, an access gate
10
is formed on the thin gate oxide
7
on the surface of the substrate
2
. As shown here, the access transistor may comprise a stack similar to the stack comprising the floating gate
6
, the isolating layer
14
and the control gate
8
, but the access gate may also comprise a structure consisting of only a single layer. Also the sidewalls of the access gate
10
are covered by an insulating spacer
11
. The drain region
3
and the source region
4
are connected to a drain line and a source line, respectively, by the respective drain contact
12
and source contact
13
.
In such prior art 2T non-volatile memory cell types arranged as a planar structure, as described above, the select gate is usually positioned next to the control gate which is arranged on the floating gate. This planar arrangement has the disadvantage that a non-volatile memory cell of this type occupies a relatively large area on the semiconductor surface. The advance of processing technologies enables structures having smaller feature sizes to be manufactured, so that the cell size of these planar 2T cells can be reduced. However, the size reduction is limited due to a number of structural constraints, e.g. minimal contact sizes, minimal spacer thickness, etc. Scaling down of the structure as shown in
FIG. 1
is limited by its design: i.e., certain minimal sizes within the structure must be maintained. Using 0.18 &mgr;m design rules, such a memory cell will typically have a size of 0.6-0.8 &mgr;m
2
.
U.S. Pat. No. 5,386,132 discloses a more compact arrangement of a Flash memory cell in
FIGS. 9A and 9B
. This non-volatile memory cell is arranged as a two-transistor (2T) vertical split channel EEPROM on a semiconductor substrate and comprises a source region, a drain region, a control gate, a floating gate and a select gate, the control gate being arranged as a pillar inside a trench. The floating gate is arranged as a tube surrounding this pillar-shaped control gate. The select gate is arranged as an annular structure surrounding the control gate in the top region of the control gate. The drain region is also arranged as an annular structure, which surrounds the control gate just below the select gate. The source region is located below the control gate pillar.
The non-volatile memory cell of U.S. Pat. No. 5,386,132 advantageously reduces the area needed on the substrate, and allows further downsizing and/or higher densities of EEPROM and FLASH memory devices.
However, the fabrication of such a non-volatile memory cell, as disclosed in U.S. Pat. No. 5,386,132, is very complex due to the application of an annular double trench structure. In particular, the separation of the respective gates by a thin oxide is difficult and may disadvantageously reduce the process yield and the reliability of the non-volatile memory cell.
Moreover, in the non-volatile memory cell of U.S. Pat. No. 5,386,132, the select gate and the control gate are interconnected. During the programming steps (write and erase) and the reading steps of such a memory cell both select gate and control gate have the same potential. Separate control of the respective gate potentials is not possible.
It is an object of the present invention to provide a semiconductor device comprising a 2T non-volatile memory cell for storing at least one bit that is more compact than planar 2T non-volatile memory cells known from the prior art. The present invention relates to a semiconductor device comprising, in a semiconductor substrate containing a first dopant type, a first non-volatile memory cell for storing a bit, comprising a first drain region in the substrate, a first floating gate, a first control gate, a first thin gate isolation layer, and an insulating layer, the insulating layer being positioned on top of the first floating gate, the first control gate being positioned on top of the insulating layer, the first floating gate being positioned on top of the first thin gate isolation layer, and further comprising a first access transistor for controlling access to the first non-volatile memory cell, wherein the first non-volatile memory cell comprises a buried layer in the substrate containing a second dopant type and a first source region, the first access transistor is formed in a first trench on the substrate, the first trench extending substantially from the first source region to the surface of the substrate, the first trench being adjacent to the first floating gate and directed in a first direction parallel to the surface of the substrate.
In comparison with a non-volatile memory cell of the prior art, the present invention provides a non-volatile memory cell with a smaller cell size.
Moreover, in a first embodiment the present invention relates to a semiconductor device as described above, comprising in the semiconductor substrate, a second non-volatile memory cell for storing a bit, comprising a second drain region in the substrate, a second floating gate, a second control gate, a second thin gate isolation layer, and a second insulating layer, the second insulating layer being positioned on top of the second floating gate, the second control gate being positioned on top of the second insulating layer, the second floating gate being positioned on top of the second thin gate isolation layer, the buried layer containing a second source region, and the device further comprising a second access transistor for controlling access to the second non-volatile memory cell, the second non-volatile memory cell being adjacent to the first non-volatile memory cell in a second direction, the second direction being parallel to the surface of the substrate and perpendicular to the first direction,
wherein the second access transistor is formed in a second trench on the substrate, the second trench extending substantially from the second source region to the surface of the substrate, the second trench being adjacent to the second floating gate and directed in the second direction, and
the first access transistor of the first non-volatile memory cell being separated from the second access transistor of the second non-volatile memory cell by an isolation gate, comprising a dummy floating gate, a dummy insulating layer and a dummy control gate, the dummy insulating layer being positioned on top of the dummy floating gate, the dummy control gate being positioned on top of the dummy insulating layer. This arrangement of two non-volatile memory cells results in a smaller total area than the area needed for two separate non-volatile memory cells.
Furthermore, a further size reduction for a 2T non-volatile memory cell is achieved by combining the select gates of two adjacent 2T non-volatile memory cells into a single select gate. In a second embodiment, the present invention relates to a semiconductor
Gebremariam Samuel A
Koninklijke Philips Electronics , N.V.
Lee Eddie
Waxler Aaron
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