Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-11-05
2004-11-02
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S734000, C257S735000, C257S737000
Reexamination Certificate
active
06812124
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 91100094, filed on Jan. 7, 2002.
BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates in general to a chip structure with bumps and a process for fabricating the chip, and more specifically relates to bumps made of specific material so that the bumping process is simplified and the manufacturing cost is reduced.
2. Description of Related Art
Recently, following the high-development of information technology, electronic products are commonly used in the public. The design fashions of various electronic products trends also generally towards lightness, thinness, shortness and smallness. Therefore, as far as the field of semiconductor packages is concerned, a lot of package structures are provided in high density type. In some fields of package, bumps are formed on a chip to perform Flip Chip Packaging or Tape Carrier Packaging. Bumps are generally divided into 2 types, one is made of solder, the other is made of gold. The bumps made of gold in prior art will be described as follows.
FIG. 1
to
FIG. 5
are schematic cross-sectional views showing the progression of steps for producing a bump made of gold in accordance with a conventional method.
As shown in
FIG. 1
, a chip
110
which has an active surface
112
and bonding pads
116
(only one bonding pad is shown) is provided. The bonding pads
116
are formed on the active surface. A passivation layer
114
is formed on the active surface
112
and a
1
a
1
exposes the bonding pads
116
so that the chip
110
is electrically connected to other outside circuit (not shown) through the bonding pads
116
. The Under Bump Metal process is followed to form a barrier layer
120
on the active surface
112
of the chip
110
by sputtering method. The barrier layer
120
covers bonding pads
116
and the passivation layer
114
. The material of the barrier layer
120
is for example TiW etc., wherein a thickness of the barrier is about thousands of angstrom. Then a seed layer
130
is formed on the barrier layer
120
by electrical plating or sputtering method. After that, the Under Bump Metal
140
is completed. The material of seed layer
130
is for example gold, wherein a thickness of the seed layer is about 1000 angstrom, and the Under Bump Metal
140
is composed of the barrier layer
120
and seed layer
130
.
As shown in
FIG. 2
, a photolithography process is performed. A photo resist layer
150
is formed on the seed layer
130
. After the photo resist layer
150
has been exposed and developed, a pattern (not shown) is transferred to the photo resist layer
150
so that openings
152
(only one opening is shown) which exposes bonding pads
116
are formed in the photo resist layer
150
.
As shown in
FIG. 3
, a bumping process follows. Bumps
160
(only one bump is shown) are filled in the openings
152
of the photo resist layer
150
, wherein the material of the bump
160
is gold.
Referring to FIG.
3
and
FIG. 4
, the photo resist layer
150
is removed from the surface of the seed layer
130
.
Referring to FIG.
4
and
FIG. 5
, the Under Bump Metal
140
which is exposed is removed by an etching method. Then an annealing process is performed so that the metal ions with defects which are in the bumps
160
are rearranged to be in a stable state.
As it is described above, the bumping process is complicated, high cost and is not so effective a manufacturing process.
SUMMARY OF INVENTION
According to the foregoing description, an object of this invention is to provide a structure and a fabricating process of a bump so that the bumping process is simplified and cost down by changing the material of the bumps.
To attain the foregoing and other aspects, the present invention proposes a chip structure with bumps comprising: a chip and at least a bump. Wherein the chip has an active surface and at least a bonding pad, and the bonding pad is formed on the active surface. The bump is disposed on the bonding pad, and the bump comprises a medium layer, a bump body and a bump body passivation layer. The medium layer is disposed on the bonding pad, and a material of the medium layer includes zinc. A bump body is disposed on the medium layer, and a material of the bump body includes nickel. A bump body passivation layer covers the bump body except for a portion of the bump body that connects to the medium layer, wherein a material of the bump body passivation layer includes gold.
Also to attain the foregoing and other aspects, the present invention proposes a process for fabricating a chip with bumps comprising the following steps. First providing a chip that has an active surface and at least a bonding pad, wherein the bonding pad exposes the active surface. Then performing an activation step, depositing a medium layer on the bonding pad. Forming at least a bump body on the medium layer in an electroless plating way, and forming a bump body passivation layer covering the bump body except for a portion of the bump body that connects to the medium layer.
According to a preferred embodiment of the present invention, the material of the bump body is nickel, and the material of the bump body passivation layer is gold. The height of the bump body is about 5 to 10 microns, and the height of the bump body passivation layer is about 1 to 3 microns. The bump body and the bump body passivation layer are formed by electroless plating.
As it is described above, the feature of the present invention is to change the material of the bumps so that the bumps can be formed on the bonding pads of a chip in a simplified manufacturing process.
REFERENCES:
patent: 2002/0017711 (2002-02-01), Kwon et al.
patent: 2002/0093096 (2002-07-01), Tago et al.
patent: 2002/0180064 (2002-12-01), Hwan et al.
patent: 2002/0185733 (2002-12-01), Chow et al.
patent: 2002/0190395 (2002-12-01), Fang et al.
patent: 2003/0067073 (2003-04-01), Akram et al.
Advanced Semiconductor Engineering Inc.
Ha Nathan W.
Jiang Chyun IP Office
Pham Long
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