Single event upset in SRAM cells in FPGAs with leaky gate...

Details Single event upset in SRAM cells in FPGAs with leaky gate... Single event upset in SRAM cells in FPGAs with leaky gate...

2003-03-25

2004-11-23

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S190000

Reexamination Certificate

active

06822894

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to circuitry resistant to single event upset (SEU).
BACKGROUND OF THE INVENTION
A programmable logic device (PLD) is a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, called a field programmable gate array (FPGA), is popular because of a superior combination of capacity, flexibility, time-to-market, and cost. An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) from an external source into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. Thus, the collective states of the individual configuration memory cells determine the function of the FPGA.
A well-studied occurrence in circuitry is called Single Event Upset (SEU). SEU is an inadvertent change in state of a circuit caused by an external energy source such as, for example, cosmic rays, alpha particles, energetic neutrons, and the like. The energetic particles may randomly strike a semiconductor device and penetrate into the semiconductor device. These particle strikes create pairs of electrons and holes, which in turn cause undesirable transients that may upset circuit elements such as, for example, flipping the logic state of a latch or other memory element. As fabrication geometries and supply voltages continue to decrease, SEU problems become more severe. As a result, efforts to reduce SEU problems are increasingly important.
In a conventional DRAM or SRAM, SEU may be addressed with well-known error correction techniques. However, error correction may not be practical for FPGA configuration memory cells. For example, because an FPGA's configuration memory cells define how the FPGA's CLBs, IOBs, and interconnect structure are configured, inadvertent state changes in the configuration memory cells resulting from SEU transients may alter how the FPGA operates.
One way to remedy SEU problems in configuration memory cells is to use triple modular redundancy (TMR). With TMR, individual memory cells are replaced with three sets of memory cells and majority voter logic, where the outcome of at least two of the three sets controls FPGA operation. However, implementing TMR in an FPGA undesirably increases the size and cost of the FPGA.
Others have attempted to increase resiliency to SEU transients. For example,
FIG. 1
shows an SEU-resistant memory cell
100
of the prior art. Memory cell
100
is a latch having cross-coupled inverters
102
and
104
coupled between complementary data terminals D and {overscore (D)}. Resistor R
1
, which is coupled between the output of inverter
102
and the input of inverter
104
, delays transients caused by SEU particle strikes that change the state of inverter
102
and prevents short transients from reaching the input (and possibly changing the state) of inverter
104
, which in turn gives inverter
104
more time to reset inverter
102
to its correct state. Similarly, resistor R
2
, which is coupled between the output of inverter
104
and the input of inverter
102
, delays transients caused by SEU particle strikes at inverter
104
from reaching the input (and possibly changing the state) of inverter
102
, which in turn gives inverter
102
more time to reset inverter
104
to its correct state.
To provide SEU resiliency, resistors R
1
and R
2
each have a resistance of between approximately 100 kilo-ohms and ten mega-ohms. Unfortunately, the formation of such large resistors may consume a relatively large amount of area and complicates integration with other structures formed using the same complementary-metal-oxide semiconductor (CMOS) processes.
Accordingly, it would be desirable and useful to provide an SEU-resistant memory circuit that consumes minimal silicon area and is suitable for integration with a CMOS process.
SUMMARY OF THE INVENTION
A latch is disclosed that includes SEU-resistant circuitry that reduces the latch's susceptibility to SEU transients without forming large resistors. In accordance with the present invention, a latch having cross-coupled inverters includes SEU-hardening resistive loads formed by transistors configured as leaky capacitors. For some embodiments, a first SEU-hardening transistor has a gate coupled to the input of a first inverter and has source and drain regions coupled to the output of a second inverter, and a second SEU-hardening transistor has a gate coupled to the input of the second inverter and has source and drain regions coupled to the output of the first inverter. The SEU-hardening transistors have relatively thin gate oxide layers that allow leakage currents between their gate and source/drain regions. These leakage currents allow the SEU-hardening transistors to appear as large resistive loads between the cross-coupled inverters. In this manner, a transient upset to one of the inverters is not readily carried to the other inverter because it is slowed by the large resistance of the SEU-hardening transistor.
The ability of the SEU-hardening transistors to appear as large resistive loads without consuming large amounts of silicon area is advantageous. By comparison, forming large resistive loads using passive resistors formed in either a polysilicon layer or in the substrate consumes much more silicon area. Further, the SEU-hardening transistors of present embodiments are easily integrated into CMOS fabrication processes.
For other embodiments, pass transistors may be added to the latch for selecting and/or addressing the latch. Also, for some embodiments, latches in accordance with present embodiments may be used as memory cells within an FPGA.


REFERENCES:
patent: 4912675 (1990-03-01), Blake et al.
patent: 6735110 (2004-05-01), Lesea

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