Method to eliminate via poison effect

Details Method to eliminate via poison effect Method to eliminate via poison effect

2001-05-31

2004-11-23

Chen, Kin-Chan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S693000, C438S694000, C438S700000

Reexamination Certificate

active

06821896

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices in general, and in particular, to a method of preventing via poisoning and the attendant “volcano” effect which can cause reliability as well functionality problems especially with sub-micron technologies.
(2) Description of the Related Art
Poisoned vias and the attendant “volcano”-like eruptions that occur at interconnections between metal layers in semiconductor devices are becoming more and more evident with newer metals, such as copper, and newer dielectrics, such as low-k dielectrics, that are gaining more use in the low sub-micron technologies of to-day. It is disclosed later in the embodiments of the present invention a method of forming interconnects, such as the damascene interconnect, without having the via poison effect.
With the advent of ultra large scale integrated (ULSI) circuit technology, the number of interconnections required between millions of transistors have increased astronomically, as is well known to the practitioners in the art. These interconnections, in the form of metal lines, are usually are of very fine geometries and are closely spaced with respect to each other in order to conserve “real estate” in the chip on which they are formed. The planar area of the chip is further conserved by forming multi-level metallized layers separated from each other by insulative layers. The close spacing between the lines, both horizontally on the same layer, and vertically between layers, can cause higher electrical interference and cross-talk between the lines, and hence high resistance-capacitance (RC) delay for the circuitry. As the device geometries shrink further to deep submicron geometries such as 0.15 micrometers (&mgr;m), the RC delay becomes even more significant.
In order to decrease the RC delay, or, time constant, within these multi-level integrated systems, low-k (dielectric constant) insulative materials are used. Conventional semiconductor fabrication methods use silicon dioxide or similar insulative materials as both gap filler between adjacent conductor lines on the same layer and as an interlayer insulator between different layers of interconnections. However, low-k materials give rise to via poison effect during the process of manufacturing interconnects, especially copper dual damascene interconnects. The present invention discloses a method of preventing such poison effects in “vias” formed between metal layers as well as in “contacts” that are formed between the devices in the semiconductor substrate and the first level metal, as is known in the art.
Cu dual damascene is preferred as an interconnect because, as is well known in the art, copper has lower resistivity than the commonly used aluminum and, therefore contributes to lower RC delay. The damascene process also provides a better control of the metal line geometries, as described below, and therefore improves further the RC characteristics of the lines. However, if the damascene structure is not properly protected during forming of the contact and via holes, the holes can be “poisoned” due to outgassing from the insulative layers, and/or due to the hydrophobic nature of the insulative layers. A poisoned contact hole (reaching the substrate), or a poisoned via hole (connecting different metallized layers) can give rise to voids, cavities for contaminants to enter, poor interfaces between contacting conductors, and, hence, poor connections between interconnects. It is disclosed later in the embodiments of the present invention a method of protecting dual damascene structures in order to avoid via poisoning problem and the attendant poison effect.
In one approach for a dual damascene process shown in
FIG. 1
a
, two insulative layers (
120
) and (
130
) are formed on a substrate (
100
) with an intervening etch-stop layer (
125
). Substrate (
100
) is provided with metal layer (
110
) and a barrier layer (
115
). Metal layer can be the commonly used aluminum or copper, while the barrier can be an oxide layer. A desired trench or trench pattern (
150
) is first etched into the upper insulative material (
130
) using conventional photolithographic methods and photoresist (
140
). The etching stops on etch-stop layer (
125
). Next, a second photoresist layer (
160
) is formed over the substrate, thus filling the trench opening (
150
), and patterned with hole opening (
170
), as shown in
FIG. 1
b
. The hole pattern is then etched into the lower insulative layer (
120
) as shown in
FIG. 1
c
and photoresist removed, thus forming the dual damascene structure shown in
FIG. 1
f.
Or, the order in which the trench and the hole are formed can be reversed. Thus, the upper insulative layer (
130
) is first etched, or patterned, with hole (
170
), as shown in
FIG. 1
d
. The hole pattern is also formed into etch-stop layer (
125
). Then, the upper layer is etched to form trench (
150
) while at the same time the etching transfers the hole pattern in the etch-stop layer into lower insulation layer (
120
), as shown in
FIG. 1
e
. It will be noted that the etch-stop layer stops the etching of the trench into the lower insulation layer. After the completion of the thusly formed dual damascene structure, both the hole opening and trench opening are filled with metal (
180
), and any excess material on the surface of the substrate is removed by chemical mechanical polishing, as seen in
FIG. 1
f.
However, when trench (
150
), or hole (
170
) openings are formed through the insulative layers (
120
) and (
130
) as shown in
FIGS. 1
b
-
1
e
, moisture (
190
) is absorbed from the atmosphere by the exposed dielectric layers on the sidewalls of the openings. After copper (
180
) is deposited, moisture (
190
) is then released from the dielectric layers. This moisture diffuses into the metal causing poisoned via/contact metallurgy.
Other forms of via poisoning and the attendant volcano effect can also occur during the processing of vias and contacts in semiconductor manufacturing, especially when interconnect holes are filled with photoresist in an attempt to protect the holes from damage during subsequent process steps. A dual damascene with a sacrificial fill is described in U.S. Pat. No. 5,705,430 by Avanzino, et al. A first layer of insulating material is formed with via openings. The openings arc filled with a sacrificial removable material. A second layer of insulating material is deposed on the first layer. In one embodiment, the etch selectivity to the etchant of the second layer is essentially the same as the sacrificial via fill and, preferably, is substantially higher than second layer. Using a conductive line pattern aligned with the via openings conductive line openings are etched in the second insulating layer and, during etching, the sacrificial fill is removed from the via openings. In a second embodiment. The sacrificial material is not etchable by the etchant for forming the conductive line openings and, after formation of the conductive line openings, the sacrificial material is removed with an etchant to which the first insulating layer is resistive or less selective. A conductive material now is deposited in die conductive line and via openings. If, however, the sacrificial fill is a photoresist, where the photoresist can be removed by any number of methods including oxygen plasma ashing, then the residues found in the via holes can cause volcano-like eruptions in later process steps. Another method of forming a dual damascene structure using a sacrificial stud in the via hole is shown in U.S. Pat. No. 6,033,977 by Gutsche, et al. However, in this case, the sacrificial material is selected from the group consisting of flowable oxide, CVD oxide and boron silicate glass.
Another method for producing a metallization level having contact and interconnect connecting the contacts is taught by Zettler, et al., in U.S. Pat. No. 5,422,309. An insulating layer wherein contact holes to regions to be contacted are opened is applied surface-wide onto a substrate. For

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