Low resistance metal interconnect lines and a process for...

Details Low resistance metal interconnect lines and a process for... Low resistance metal interconnect lines and a process for...

2001-11-27

2004-11-09

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S657000, C438S687000, C438S688000

Reexamination Certificate

active

06815342

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to integrated circuits (ICs) and the methods for fabricating them. More specifically, the present invention relates to the metal interconnect lines within ICs and methods for fabricating them.
BACKGROUND OF THE INVENTION
The use of copper (Cu) to fabricate interconnect lines in semiconductor devices (e.g., ICs) is known and has become increasingly common as IC feature size has decreased. Many factors have driven the switch to Cu interconnect lines, with their intrinsically low resistance per unit volume, including the decrease in IC feature size, increasing IC circuit density, the trend to lower IC operating voltages and increasing IC operating frequencies.
A known method for creating Cu interconnect lines is shown in
FIGS. 1
a
through
1
d
. Before the process begins, a thick dielectric layer
11
has been deposited on the top surface of a partially formed semiconductor device
10
. Dielectric layer
11
was then masked and etched, creating the channels in which Cu interconnects
13
will run. A conducting material such as Ta or TaN is then deposited as a barrier material. A thin layer of Cu can then be deposited as a seed layer to improve the uniformity of the subsequent electroplated Cu. Cu was electroplated onto the IC and then planarized by chemical-mechanical polishing (CMP) to form Cu interconnect
13
. The deposition of barrier layer
15
, typically composed of a dielectric material such as silicon carbide (SiC) or silicon nitride (SiN), followed by the deposition of passivation layer
17
created the structures illustrated in
FIG. 1
a.
As shown in
FIG. 1
b
, after a masking step, an etching step creates an opening
16
to Cu interconnect
13
. A barrier layer
18
, typically formed from tantalum (Ta) or tantalum nitride (TaN) followed by an aluminum layer
19
is then deposited into opening
16
using any one of several known semiconductor processing techniques, as illustrated in
FIG. 1
c
. Another pad masking step and another etching step follow the deposition of Al layer
19
, creating the final bond pad, as shown in
FIG. 11
d
The bond pads of the IC must still be formed from Al, as the packaging process is not mature enough to wire directly to Cu.
As
FIGS. 1
a
through
1
d
only show a cross-section of the Cu interconnect lines, it should be stated that these interconnect lines form relatively long, linear structures which couple together at least two bond pads, and frequently many more bond pads. As these interconnect structures are well known, no illustration of them beyond the given cross-sections is needed to understand and implement the present invention.
In order to create a Cu interconnect of sufficient thickness to have the desired low resistance for reducing voltage drop from the power pads into the center of the die, the Cu interconnects must typically be approximately 3 to 4 microns thick. Unfortunately, the creation of such thick Cu interconnects is expensive. The deep etch and thick Cu deposition required to create such thick interconnects (
FIG. 1
a
) is expensive and time consuming. It is also difficult to insure that Cu will fill the etched area completely to create the interconnect lines, and cracking and delaminations during the deposition process are common problems. It is also not possible to control the CMP step as precisely as is desired, and process variations can result in Cu thickness varying over 20-30% due, in particular, to dishing. To insure that the finished Cu interconnect lines have the required resistance value, they must be designed and made even thicker to compensate for the process variability. Interconnects which provide roughly the same low resistance as thick Cu, but which are easier to fabricate would be a desirable improvement.
SUMMARY OF THE INVENTION
In a first embodiment of the present invention, a method for fabricating low resistance interconnect lines in semiconductor devices is disclosed, wherein the lines are formed from a first Cu layer and a second Al layer. After the semiconductor device wafer has been prepared with Cu bond pad areas and Cu interconnect line channels, a layer of Al is deposited on both these bond areas and interconnect line channels. By adjusting the relative thickness of the Al and Cu in the interconnect lines, the resistance of the lines can be adjusted to meet particular requirements, and processing conditions can be optimized. As a two metal process is unavoidable in any case where Cu interconnects are created (the bond pads at least require an Al layer), the formation of the interconnects from both Cu and Al does not introduce any additional process complexity. The process to fabricate these lines requires no more steps than known processes to create thick Cu lines and their bond pads and uses no new materials. An additional advantage of the present invention is that fuses needed for memory repair in IC memory devices can be easily incorporated into the process flow described by the present invention.


REFERENCES:
patent: 5227335 (1993-07-01), Holschwander et al.
patent: 5595937 (1997-01-01), Mikagi
patent: 5939788 (1999-08-01), McTeer
patent: 5976975 (1999-11-01), Joshi et al.
patent: 5994775 (1999-11-01), Zhao et al.
patent: 6054172 (2000-04-01), Robinson et al.
patent: 6054173 (2000-04-01), Robinson et al.
patent: 6117782 (2000-09-01), Lukanc et al.
patent: 6126989 (2000-10-01), Robinson et al.
patent: 6204179 (2001-03-01), McTeer
patent: 6274486 (2001-08-01), Rhodes et al.

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