Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-24
2004-02-17
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
28, 28
Reexamination Certificate
active
06693334
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device provided with, for example, a macro cell having a multi-layer construction.
The present application claims priority of Japanese Patent Application No. 2001-225204 filed on Jul. 25, 2001, which is hereby incorporated by reference.
2. Description of the Related Art
A semiconductor integrated circuit device such as a system LSI (Large Scale Integrated Circuit) has such a configuration that a plurality of macro cells having a specific function is formed on a substrate. In each of the macro cells, such elements are formed as a transistor, a resistor, a capacitor, or a like, which are combined to make up a memory circuit of a RAM/DRAM, a variety of operation circuits, or a like.
The macro cells are supplied with power through a power wiring formed in a wiring region provided outside a macro cell region, in which wiring region is also formed a signal wiring for transmitting a signal between these macro cells.
For example, Japanese Patent Application Laid-open No. 2000-307063 discloses a technology for arranging ring-shaped wiring layers
105
and
106
for supplying power such that ring-shaped wiring layers
105
and
106
surround respectively a macro cell
104
having a multi-layer wiring-construction made up of three wiring layers
101
,
102
, and
103
as shown in
FIGS. 13 and 14
. These ring-shaped wiring layers
105
and
106
are connected to a power wiring or a ground wiring of at least one of other macro cells and functional blocks which are disposed around the macro cell
104
.
Furthermore, Japanese Patent Application Laid-open No. Hei 09-107070 discloses a technology for providing a ring-shaped diffused layer surrounding a macro cell. In a macro cell
201
having a multi-layer wiring-construction, as shown in
FIG. 15
, a substrate
202
is mounted thereon with a power wiring for other macro cells and functional blocks, ring-shaped wiring layers
203
and
204
connected to the ground wiring and also mounted therein with a ring-shaped diffused layer
205
below these ring-shaped wiring layers
203
and
204
.
This diffused layer
205
is biased as connected to the ring-shaped wiring layer
203
(
204
) connected to no other elements of the macro cell
201
, thus absorbing noise occurring in the macro cell
201
.
As the LSI processes improve in fine patterning and integration density, however, coupling capacitance between adjacent signal lines increases to have a non-negligible adverse effect on the circuit reliability; nevertheless, the above-mentioned conventional technologies have no measures to prevent noise from propagating, for example, between a signal wiring in a macro cell and an adjacent external signal wiring.
Although the above-mentioned technology disclosed in Japanese Patent Application Laid-open No. 2000-307063 can prevent noise on the power wiring or the ground wiring of the macro cell
104
from propagating through the ring-shaped wiring layers
105
and
106
to any other macro cells, functional blocks, or signal wirings disposed around the macro cell
104
, it has a problem that an external signal wiring, if any, adjacent to an internal signal wiring of the macro cell
104
permits the noise to propagate owing to coupling capacitance generated between these wirings, thus causing the malfunctioning of the macro cells or the functional blocks or the retardation and inversion of a signal through the signal wiring.
That is, if a wiring layer
110
of the external signal line of the macro cell
104
is close to its signal line wiring layers
107
,
103
, and
109
at its predetermined position as shown in
FIG. 16
, coupling capacitance occurs which is proportional to a distance of a parallel going section where, for example, the wiring layer
109
and the wiring layer
110
are close to each other and also which is roughly inversely proportional to a logarithm of a spacing between the two as shown in FIG.
17
.
This coupling capacitance causes noise to propagate between, for example, the wiring layers
109
and
110
to cause useless retardation or mistaken inversion of the signal in a logic circuit
111
a
(
111
b,
111
c,
111
d
) such as shown in
FIG. 17
, for example, thus having a worse influence as a clock signal frequency becomes larger.
Although the technology disclosed in Japanese Patent Application Laid-Open No. Hei 9-107070, on the other hand, can prevent noise from propagating through the substrate
202
, it still has a problem that the above-mentioned coupling capacitance which occurs between the adjacent signal wirings causes to noise to propagate, thus causing the malfunctioning of the adjacent macro cells or the functional blocks or the retardation or inversion of the signal along the signal wiring.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a high-reliability semiconductor integrated circuit device that can block the propagation of noise that occurs in a macro cell, to thereby prevent the noise from having an adverse effect on the adjacent macro cells, the adjacent functional blocks and adjacent signal wirings.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device including:
a functional block in which a plurality of semiconductor elements is formed on a semiconductor substrate and connected with each other by a multi-layer wiring; and
a multi-layer shield portion which is arranged so as to surround the functional block and in which shielding wiring layers are stacked vertically via an inter-layer insulation film,
wherein the multi-layer shield portion is provided with a plurality of via contacts for interconnecting vertically positioned ones of the plurality of shielding wiring layers of the multi-layer shield portion.
In the foregoing, a preferable mode is one wherein the functional block is a macro cell.
A preferable mode is one wherein the via contacts are provided in a circumferential direction of the shielding wiring layers of the multi-layer shield portion with a predetermined spacing therebetween.
A preferable mode is one wherein the via contacts are provided so as to be connected with each other from an uppermost shielding wiring layer to a lowermost shielding wiring layer making up the multi-layer shield portion at an approximately same position as viewed in a plane.
A preferable mode is one wherein the multi-layer shield portion has a notch through which a wiring layer can pass so as to connect to a terminal provided in the functional block.
A preferable mode is one wherein each of the shielding wiring layers of the multi-layer shield portion is formed in a same layer as corresponding one of the multi-layer wirings of the functional block.
A preferable mode is one wherein the multi-layer shield portion is supplied with a predetermined potential but has each of the shielding wiring layers thereof not connected to a power supply terminal or a ground terminal connected to the semiconductor elements formed in the functional block.
A preferable mode is one that wherein further includes a plate-shaped shield portion formed of a plate-shaped shielding wiring layer that covers a top surface of the functional block partially or completely.
A preferable mode is one that wherein the plate-shaped shield portion is supplied with a predetermined potential but not connected to the power supply terminal or the ground terminal connected to the semiconductor elements formed in the functional block.
A preferable mode is one that wherein a tunnel-shaped shield portion is provided in the functional block for accommodating an external wiring layer connected to a circuit outside the functional block in such a manner that the external wiring layer may pass through the functional block along the semiconductor substrate; and
the tunnel-shaped shield portion is provided along a wiring path of the external wiring layer above the external wiring layer, having an upper-part shielding wiring layer consisting of an elo
Abraham Fetsum
NEC Electronics Corporation
LandOfFree
Semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3325075