Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
2000-10-13
2004-06-15
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S611000, C345S613000, C345S614000
Reexamination Certificate
active
06750869
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of data processing in a computer graphics system. More specifically, the present invention pertains to an anti-aliasing buffer architecture for processing fragments in a computer graphics system.
2. Background Art
Computer graphics generally consists of instructions implemented via a graphics system executed on a computer system. The instructions are used to specify the calculations and operations needed to produce rendered images that have a three-dimensional appearance.
The computer graphics system can be envisioned, in part, as a pipeline through which pixel data pass. The data are used to define the image to be produced and displayed. At various points along the pipeline, various calculations and operations are specified by the graphics designer, and the data are modified accordingly.
In the initial stages of the pipeline, the desired image is composed using geometric shapes such as lines and polygons, referred to in the art as geometric “primitives.” The derivation of the vertices for an image and the manipulation of the vertices to provide animation entail performing numerous geometric calculations in order to project the three-dimensional world being designed to a position in the two-dimensional world (the “view plane”) of the display screen.
Primitives are then decomposed into “fragments,” and these fragments are assigned attributes such as color, perspective, and texture. In order to enhance the quality of the image, effects such as lighting, fog, and shading are added, and anti-aliasing and blending functions are used to give the image a smoother and more realistic appearance. In the final image generation stage, the fragments and their associated attributes are stored in the frame buffer as pixels. The pixel values can be later read from the frame buffer, and can be used to display images on the computer screen.
The entire process, from projecting the primitives onto the view plane through formation of the output image, is known as rendering. The specific process of decomposing individual primitives and determining per-pixel or per-fragment values from those geometric primitives is known as rasterization.
With reference now to Prior Art
FIG. 1
, process
130
exemplifies one embodiment of a graphics design process implemented using a graphics program on a computer system. Process
130
operates on vertex (or geometric) data
131
. The blocks within process
130
consist of display list
133
, evaluators
134
, per-vertex operations and primitive assembly
135
, rasterization
138
, per-fragment operations
139
, and frame buffer
140
.
Vertex data
131
are loaded from the computer system's memory and saved in display list
133
; however, in some graphics programs, a display list is not used and, instead, the vertex data are processed immediately. When display list
133
is executed, evaluators
134
derive the coordinates, or vertices, that are used to describe points, lines, polygons, and the like (e.g., primitives). All geometric primitives are eventually described by collections of vertices.
With reference still to Prior Art
FIG. 1
, in per-vertex operations and primitive assembly
135
, vertex data
131
are converted into primitives that are assembled to represent the surfaces to be graphically displayed. Some vertex data (for example, spatial coordinates) are transformed, typically using matrix multiplication, to project the spatial coordinates from a position in the three-dimensional world to a position on the display screen.
In addition, advanced features are also performed in per-vertex operations and primitive assembly
135
. Texturing coordinates may be generated and transformed. Lighting calculations are performed using the transformed vertex, the surface normal, material properties, and other lighting information to produce a color value. Perspective division, which is used to make distant objects appear smaller than closer objects in the display, also occurs in per-vertex operations and primitive assembly
135
.
Rasterization
138
is the conversion of vertex data into “fragments.” Each fragment corresponds to a single element (e.g., a “pixel”) in the graphics display, and typically includes data defining color, shading, and texture. Per-fragment operations
139
consist of additional operations that may be enabled to enhance the detail of the fragments, such as blending, dithering and other like operations. After completion of these operations, the processing of the fragment is complete and it is written as a pixel to frame buffer
140
.
Part of the process of anti-aliasing is performed during rasterization
138
. Anti-aliasing is a technique for correcting the problem of aliasing, which can cause the edges of an object to appear jagged when the object is rendered. For example, a polygon may only partially cover a number of pixels; that is, the edge of the polygon may pass through a number of adjacent pixels. If these pixels are approximated as being fully covered by the polygon (and are colored the color of the polygon), the edge the polygon would likely appear as jagged when it is rendered. In addition, the fragments that correspond to each screen pixel must be kept in a sorted order according to their distance from the view plane.
In general, there are two common approaches for implementing this sorted ordering: the “Z-buffer” approach and the “A-buffer” approach. In the Z-buffer approach, pixel data including a depth value (e.g., a z-dimension indicating distance from a view plane) are stored for every pixel location in a display image. As geometric primitives are rasterized, the depth values for newly generated pixel data are compared to depth values for pixel data in the Z-buffer. If the newly generated pixel data are closer to the view plane (e.g., a smaller value of z), then these data are written over the current pixel data in the Z-buffer. If the newly generated pixel data have a larger value of z, then the new data are disregarded.
The Z-buffer approach will always result in aliasing because it does not adequately address partially covered pixels. The A-buffer approach improves the Z-buffer approach by addressing anti-aliasing for partially covered pixels.
In the A-buffer approach, polygons are clipped into fragments at the boundaries of a pixel. For example, consider a square-shaped pixel partially covered by a portion of a polygon. A pixel fragment would be generated to represent the portion of the polygon covering the pixel. A bit mask representing the edges of the polygon is used to describe how the polygon partially covers the pixel. When there are multiple polygons contributing to the color of a pixel, multiple pixel fragments are generated, and the colors of the fragments are then resolved within the A-buffer to compute a final color for the pixel. The multiple fragments corresponding to a pixel location are stored in memory as a “fragment stack.”
Prior Art
FIG. 2
is a data flow diagram showing one embodiment of an anti-aliasing buffer (A-buffer) architecture
200
used in a computer graphics system. In A-buffer architecture
200
, the fragment data flow in a loop from fragment memory
210
to fragment manager
220
, through fragment evaluation pipeline
230
a
or
230
b
, then back to fragment memory
210
. The process may also be performed using parallel paths, each path with distinct fragment memory, fragment manager, evaluation pipeline(s), and result router.
A new fragment
202
for a particular pixel location causes fragment stack
212
for that pixel location to be read from fragment memory
210
. Fragment manager
220
feeds fragment stack
212
to one of the fragment evaluation pipelines
230
a
or
230
b
(it is appreciated that more than two pipelins can be used in A-buffer architecture
200
).
After evaluation in the pipeline, the final pixel color for the pixel location is determined, and pixel data
246
(comprising the pixel color and pixel location) are sent to frame buffer
140
via evaluation result router
24
Nguyen Hau
Tung Kee M.
Wagner , Murabito & Hao LLP
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