Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-03
2004-08-31
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S287000, C257S493000, C257S401000, C438S589000
Reexamination Certificate
active
06784505
ABSTRACT:
FIELD OF INVENTION
This invention relates to semiconductor power devices and their fabrication, and more specifically to low-voltage vertical MOSFET power devices.
DISCUSSION OF PRIOR ART
Recently, the personal portable electronics field, including such devices as cellular phones and notebook computers, has experienced explosive growth. The systematic reduction of supply voltage, accompanied by a corresponding decrease in device feature size and high system performance, has become a primary focus for the development of more advanced power devices. The voltage scaling of the total system requires that the power MOSFETs used in power management circuitry can be efficiently turned on and off at a low gate drive voltage. In order to meet this requirement, the power semiconductor switches should have a low level threshold voltage (less than 1.0 volts). See FIG.
1
. To lower the threshold voltage, the prior art uses a low implant dose in P-well
30
plus a thinner gate oxide
40
. This approach achieves a low gate rating, but it may result in a high channel leakage current and a poor high-temperature performance. Due to the low total net charges of the well, this approach also makes the device susceptible to punch-through breakdown. In addition, the doping in the channel is non-uniform.
Another recently-disclosed prior-art technique (shown in
FIG. 2
) employs the P-type epi-layer
70
forming the channel region of the device. The drift region
25
of the device is formed by implanting the opposite-type dopant into the trench bottom
55
, followed by a thermal annealing step. Consequently, the doping concentration of the channel region is determined by the doping concentration of the epi-layer
70
, and the doping profile along the device channel is uniform. This yields a higher total net charge located in the well for a given threshold voltage. Thus, the device's performance and off-state breakdown characteristics are expected to be improved. In this prior art, adjacent drift regions
25
clearly are not allowed to merge. The regions are kept separated to provide so-called “bulk resurf”, so that the on-resistance of the device drift region
25
can be dramatically reduced [1]-[3].
As is well-known in the art, for low voltage power devices (for example, 30 volts or less) the on-resistance contribution from the drift region
25
is a very small portion of the total on-resistance. The most significant component of the device on-resistance is the resistance of the device channel region. In order to lower the channel resistance, the most efficient approach is to reduce the device unit cell pitch and increase the channel density. Unfortunately, the non-merging condition imposed on the drift regions
25
as taught in the prior art limits the minimum cell pitch and maximum channel density that the device can employ. As the result, the on-resistance of the prior art is high when used for a low voltage application. In addition, it is clear from
FIG. 2
that the prior art creates more PN junction area of the device's body-diode, resulting in a high output capacitance. Also, the parasitic BJT of the body-diode has a significantly non-uniform base width. This will degrade the body-diode forward conduction and reverse recovery characteristics. [4]
SUMMARY
The invention merges together the drift regions in a low-power trench MOSFET device via a dopant implant through the bottom of the trench. The merged drift regions permit use of a very small cell pitch, resulting in a very high channel density and a consequent significant reduction in the channel resistance. By properly choosing the implant dose and the annealing parameters of the drift region, the channel length of the device can be closely controlled, and the channel doping may be made highly uniform. In comparison with a conventional device, the invention's threshold voltage is reduced, its channel resistance is lowered, and its drift region on-resistance is also lowered. To implement the merged drift regions, the invention incorporates a new edge termination design, so that the PN junction formed by the P epi-layer and the N
+
substrate can be terminated at the edge of the die.
When compared to the prior art devices of
FIG. 1
, the more heavily P-type epitaxial layer of
FIG. 2
reduces on resistance. In addition, the separated drift regions of
FIG. 2
provide depletion regions to sustain a higher reverse voltage across the device. However, the requirement of the separated drift regions inherently reduces the density of the cells in a device. The invention provides low on resistance by using a more highly doped P-type epitaxial layer and has a higher cell density by allowing the drift regions to merge. Even with merged drift regions there is still adequate depletion to support high reverse biases. With the invention, the P-doping in the channel is more constant than the doping in prior art channels with epitaxial layers and separated drift zones. The invention provides devices with greater cell density and lower junction capacitance than devices made with separated resurf regions.
REFERENCES:
patent: 4754310 (1988-06-01), Coe
patent: 5072266 (1991-12-01), Bulucea et al.
patent: 5216275 (1993-06-01), Chen
patent: 5569949 (1996-10-01), Malhi
patent: 5665996 (1997-09-01), Williams et al.
patent: 5674766 (1997-10-01), Darwish et al.
patent: 6040212 (2000-03-01), Kim
patent: 6462376 (2002-10-01), Wahl et al.
Fairchild Semiconductor Corporation
Flynn Nathan J.
Law Office of Thomas R. FitzGerald
Roach, Esq. Laurence S.
Wilson Scott R.
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