Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2004-02-02
2004-12-07
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S338000, C257S488000, C438S302000, C438S303000, C438S304000, C438S305000, C438S306000
Reexamination Certificate
active
06828629
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-053330, filed on Feb. 28, 2003, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device successfully reduced in the off-leakage current, and a method of fabricating the semiconductor device.
2. Description of the Related Art
Recent demands for downsizing of chips have accelerated shortening of gate length of MOS transistors. Short-gate-length MOS transistors are used for battery-powered electronic appliances such as cellular phones, for which a small off-leakage current is an essential feature, and have extension layers and pocket layers formed therein by using As, having a small coefficient of diffusion, as an N-type impurity. More specifically, As is used as an N-type impurity in the pocket layers of P-channel (PMOS) transistor, and extension layers of N-channel (NMOS) transistors. For the purpose of suppressing short-channel effect, and in particular of suppressing generation of off-leakage current and lowering in threshold voltage, which are possibly accompanying the shortening of the gate length, one known conventional method is to raise impurity concentration in the channel.
In this method applied to fabrication of an NMOS transistor, first as shown in
FIG. 22A
, a gate insulating film
102
and a gate electrode
103
are formed on a semiconductor substrate
101
having a P-type well already formed therein. Next, as shown in
FIG. 22B
, boron (B) ions are implanted to the semiconductor substrate
101
to thereby form in the surficial portion thereof a P-type pocket layer
104
. The ions are implanted by oblique ion implantation which is effected from four directions normal to one another in a plan view, at an implantation energy of 5 to 10 keV, and a dose per direction of 3×10
12
to 1.8×10
13
cm
−2
. Next, as shown in
FIG. 22C
, arsenic (As) ions are implanted to the pocket layer
104
to thereby form in the surficial portion thereof an N-type extension layer
106
. The ion implantation at this time is effected from the direction normal to the surface of the semiconductor substrate
101
. The implantation energy is set to 2 to 5 keV, and the dose to 5×10
14
to 3×10
15
cm
−2
. Thereafter a deep N-type source-and-drain diffusion layer and so forth are formed, to thereby complete the NMOS transistor.
On the other hand, in this method applied to fabrication of a PMOS transistor, first as shown in
FIG. 23A
, a gate insulating film
132
and a gate electrode
133
are formed on a semiconductor substrate
131
having an N-type well already formed therein. Next, as shown in
FIG. 23B
, arsenic (As) ions are implanted in the semiconductor substrate
131
to thereby form in the surficial portion thereof an N-type pocket layer
134
. The ions are implanted by oblique ion implantation which is effected from four directions normal to one another in a plan view, at an implantation energy of 40 to 80 keV, and a dose per direction of 3×10
12
to 1.5×10
13
cm
−2
. Next, as shown in
FIG. 23C
, B ions are implanted to the pocket layer
134
to thereby form in the surficial portion thereof a P-type extension layer
136
. The ion implantation at this time is effected from the direction normal to the surface of the semiconductor substrate
131
. The implantation energy is set to 0.2 to 0.5 keV, and the dose to 5×10
14
to 2×10
15
cm
−2
. Thereafter a deep P-type source-and-drain diffusion layer and so forth are formed, to thereby complete the PMOS transistor.
Prior arts are disclosed in Japanese Patent Laid-Open Nos. 11-163157, 5-267331, 6-224381, 6-338591 and 2000-196077.
Raising in the impurity concentration in the channel by forming the pocket layer in recent transistors having a gate length reduced to as short as 100 nm or less, however, intensifies the electric field at the PN junction in the vicinity of the extension layer, and increases band-toband tunnel leakage between the drain and the body. The tunnel leakage undesirably increases the off-leakage current.
The present invention is conceived considering the above-described problems, and objects thereof reside in providing a semiconductor device capable of fully suppressing the off-leakage current even if the gate length is as short as 100 nm or less, and in providing a method of fabricating the semiconductor device.
SUMMARY OF THE INVENTION
After thorough investigations for solving the above-described subjects, the present inventors reached several embodiments described in the next.
A first semiconductor device according to the present invention comprises: a semiconductor substrate; a gate insulating film and a gate electrode formed on the semiconductor substrate: a pair of first sidewall insulating films formed on the lateral portions of the gate electrode; and a pair of second sidewall insulating films formed so as to sandwich the first sidewall insulating films with the gate electrode, and having a width larger than that of the first sidewall insulating films. In the surficial portion of the semiconductor substrate, a pair of first N-type impurity-diffused layers containing phosphorus are formed at a first depth so as to be self-aligned with respect to the gate electrode and the first sidewall insulating films. In the surficial portion of the semiconductor substrate, a pair of second N-type impurity-diffused layers are formed at a second depth deeper than the first depth so as to be self-aligned with respect to the gate electrode, the first sidewall insulating films and the second sidewall insulating films. Between the pair of second N-type impurity-diffused layers, a pair of P-type impurity-diffused layers are formed so as to respectively be in adjacent to each of the pair of first N-type impurity-diffused layers.
A second semiconductor device according to the present invention comprises: a semiconductor substrate; a gate insulating film and a gate electrode formed on the semiconductor substrate; and a pair of sidewall insulating films formed on the lateral portions of the gate electrode. In the surficial portion of the semiconductor substrate, a pair of first P-type impurity-diffused layers are formed at a first depth so as to be self-aligned with respect to the gate electrode. In the surficial portion of the semiconductor substrate, a pair of second P-type impurity-diffused layers are formed at a second depth deeper than the first depth so as to be self-aligned with respect to the gate electrode and the sidewall insulating films. Between the pair of second P-type impurity-diffused layers, a pair of N-type impurity-diffused layers containing phosphorus are formed so as to respectively be in adjacent to each of the pair of first P-type impurity-diffused layers.
In a first method of fabricating a semiconductor device of the present invention, first, a gate insulating film and a gate electrode are formed on a semiconductor substrate. Next, a pair of P-type impurity-diffused layers are formed by introducing a P-type impurity into the surficial portion of the semiconductor substrate with using the gate electrode as a mask, and a pair of first sidewall insulating films are formed on the lateral portions of the gate electrode. Here, the pair of first sidewall insulating films may be formed before the pair of P-type impurity-diffused layers are formed. Next, a pair of first N-type impurity-diffused layers are formed at a first depth by introducing at least phosphorus into the surficial portion of the semiconductor substrate with using the gate electrode and the first sidewall insulating films as a mask. Next, a pair of second sidewall insulating films are formed so as to sandwich the first sidewall insulating films with the gate electrode, and so as to have a width larger than that of the first sidewall insulating films. Next a pair of second N-type impurity-diffused layers are for
Abraham Fetsum
Fujitsu Limited
Westerman Hattori Daniels & Adrian LLP
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