Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-01-28
2004-06-01
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185250, C365S189090, C365S207000
Reexamination Certificate
active
06744673
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of electrically programmable and electrically erasable read-only memories, and more particularly, to a fast-sensing amplifier for a flash memory device.
BACKGROUND OF THE INVENTION
In recent years, the use of personal computers has grown tremendously in nearly all aspects of society. Personal computers typically comprise a microprocessor chip, random access memory, and non-volatile memory. Non-volatile memory is memory that retains its stored information even when power is no longer supplied to the chip. One type of non-volatile memory is flash memory, which can be both erased and programmed electrically.
In non-volatile complementary metal-oxide semiconductor (CMOS) read-only flash memories employing floating-gate memory devices, a memory array consisting of a number of these devices is customarily coupled to a common sensing circuit through a column line connecting the drains of the individual memory devices and a word line connecting the gates of the devices in the array, to comprise a memory circuit. Typically a charged column line remains charged if the memory device coupled to it is nonconductive. If coupled to a conductive memory device, the line discharges. The sensing circuit, or amplifier, determines the binary state (conductive or nonconductive) of the memory device based on whether the line is charged or not.
A floating-gate memory device typically requires limiting the maximum potential at the column line to a potential significantly less than the voltage applied to the word line during read, or sense, operations. This minimizes disturbing the data stored on the floating gate of a device during read operations. Usually within a non-volatile flash memory device, the voltage swing on the column line between a high binary state and a low binary state is quite small. This reduction in voltage swing on the capacitive load on the column line of the memory array decreases the access time needed to determine the binary state of a device, but brings about the need for an amplifier circuit to further separate the swing between a low binary state and a high binary state. The amplifier circuit also limits the maximum voltage at the column line during read operations. Although using an amplifier circuit itself adds an amplifying step that increases access time, the net effect still serves to decrease access time as compared to a memory circuit with no amplifier but having a large voltage swing on the large capacitance of the memory column lines. This is because minimizing the voltage swing between a high and low binary state typically reduces read-access time more than the inclusion of an amplifying step increases access time.
FIG. 1A
is a system-level depiction of one prior art approach to CMOS high-speed sensing. The sensing circuit, or amplifier, consists of two read-biasing and amplifying circuits coupled to a differential amplifier. Generally, after the column line of a desired memory device within the memory array is selected, the differential amplifier compares the charge, or voltage, of the selected device to a sensing-reference charge, or voltage. The differential amplifier amplifies the difference between the voltage at the selected memory device and the sensing-reference voltage. This difference corresponds to the binary state of the device.
In a typical read, or sensing, operation, the column line of the memory array often discharges substantially when coupled to a conductive memory device. Before another read cycle can occur, the line must be recharged. The recharging period retards access time in these memory circuits because of the considerable parasitic capacitance generally associated with the lines. The greater capacitance of longer lines exacerbates this problem in larger memory circuits. A drawback of the prior art is that the capacitance of the reference column effectively doubles the capacitance that needs to be recharged. In some instances, this delays access time over the time needed just to recharge the column line of the selected memory device.
FIG. 1B
depicts in further detail one prior art approach to implementing the read-biasing and amplifying circuit in FIG.
1
A. Transistors P
1
, P
2
, P
3
, N
1
, N
2
, and N
3
make up a typical amplifier with feedback biasing, to maintain the selected column line at a stable voltage during sensing. Prior to a read operation, CP, a clock pulsed high, discharges the selected column line to ground. During this time, transistor N
12
isolates the column line of the selected memory device from the biasing circuit. Upon CP going low, the memory device reconnects to the biasing circuit, and transistor N
2
quickly charges the column line to near the sensing-reference level. The feedback path then turns N
2
off and current-loading transistor P
3
supplies the final charging current.
Another drawback to the prior art is the complexity of this read-biasing and amplifying circuit. The large number of transistors in the amplifying circuit, consisting of transistors N
1
, N
2
, N
3
, P
1
, P
2
, and P
3
, lengthens memory read-access time due to the parasitic capacitances of the transistors themselves and the delays they cause. Still another drawback is that isolating the memory array from the biasing circuit before a read operation via transistor N
12
further delays read-access time. Moreover, N
12
loads the circuit with additional capacitance, which also increases access time.
SUMMARY OF THE INVENTION
The present invention provides for a fast and efficient MOS sensing amplifier for sensing the binary state of floating-gate memory devices within a floating gate memory array having a column line selectively coupled to the devices. Prior to sensing, the column line discharges quickly to ground. During a sense operation, a read-biasing and amplifying circuit quickly pulls up the column line to the sense potential at the selected memory device. A differential amplifier compares this sensed potential to a sense-reference potential, providing as output the binary state of the selected memory device.
The above summary of the present invention is not intended to present each embodiment or every aspect of the present invention. This is the purpose of the figures and the associated description that follow.
REFERENCES:
patent: 4223394 (1980-09-01), Pathak et al.
patent: 4250570 (1981-02-01), Tsang et al.
patent: 4389715 (1983-06-01), Eaton, Jr. et al.
patent: 4459685 (1984-07-01), Sud et al.
patent: 4606052 (1986-08-01), Hirzel et al.
patent: 4654831 (1987-03-01), Venkatesh
patent: 4807191 (1989-02-01), Flannagan
patent: 4881200 (1989-11-01), Urai
patent: 4885720 (1989-12-01), Miller et al.
patent: 4975883 (1990-12-01), Baker et al.
patent: 5053990 (1991-10-01), Kreifels et al.
patent: 5077738 (1991-12-01), Larsen et al.
patent: 5163023 (1992-11-01), Ferris et al.
patent: 5177745 (1993-01-01), Rozman
patent: 5191552 (1993-03-01), Nakai et al.
patent: 5197028 (1993-03-01), Nakai
patent: 5222046 (1993-06-01), Kreifels et al.
patent: 5222076 (1993-06-01), Ng et al.
patent: 5241505 (1993-08-01), Hashimoto
patent: 5253210 (1993-10-01), Terada
patent: 5258958 (1993-11-01), Iwahashi et al.
patent: 5262984 (1993-11-01), Noguchi et al.
patent: 5265054 (1993-11-01), McClure
patent: 5287310 (1994-02-01), Schreck et al.
patent: 5293088 (1994-03-01), Kasa
patent: 5293333 (1994-03-01), Hashimoto
patent: 5293345 (1994-03-01), Iwahashi
patent: 5301149 (1994-04-01), Jinbo
patent: 5305273 (1994-04-01), Jinbo
patent: 5306963 (1994-04-01), Leak et al.
patent: 5307317 (1994-04-01), Shiraishi et al.
patent: 5335198 (1994-08-01), Van Buskirk et al.
patent: 5339272 (1994-08-01), Tedrow et al.
patent: 5343439 (1994-08-01), Hoshino
patent: 5381374 (1995-01-01), Shiraishi et al.
patent: 5386158 (1995-01-01), Wang
patent: 5388078 (1995-02-01), Arakawa
patent: 5414829 (1995-05-01), Fandrich et al.
patent: 5430859 (1995-07-01), Norman et al.
patent: 5463757 (1995-10-01), Fandrich et al.
patent: 5477499 (1995-12-01), Van Buskirk et al.
patent: 5500810 (1996-03-01), Shou et al.
pa
Dinh Son T.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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