Unitary interconnection structures integral with a...

Details Unitary interconnection structures integral with a... Unitary interconnection structures integral with a...

2003-04-30

2004-10-19

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S598000

Reexamination Certificate

active

06806180

ABSTRACT:

CLAIM FOR PRIORITY
The present application is related to and claims priority from Korean Application No. 2002-44226, filed Jul. 26, 2002, the disclosure of which is incorporated herein as if set forth in its entirety.
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and methods of fabricating semiconductor devices, more specifically, the present invention relates to interconnection structures for semiconductor devices.
BACKGROUND OF THE INVENTION
A semiconductor integrated circuit (IC) typically includes electrically isolated elements, such as a transistor formed at a substrate, a contact hole, and an interconnection selectively connecting the otherwise isolated elements. For example, the contact hole and the interconnection may connect a first active region to a second active region, a first gate electrode to a second gate electrode and/or a gate electrode to active region as needed.
FIG. 1A
is a cross-sectional view illustrating a conventional interconnection structure. In
FIG. 1A
, the region A illustrates an interconnection between active regions, the region B illustrates an interconnection between gate electrodes, and the region C illustrates an interconnection of a gate electrode to an active area. Referring to
FIG. 1A
, in the region A, a field region
6
is disposed in the substrate
2
to define a first active region
16
a
and a second active region
16
b
that are doped with impurities. An interlayer dielectric
20
is provided on the substrate
2
. Contact plugs
22
that electrically connect to the active regions
16
a
and
16
b
are formed through the interlayer dielectric
20
. An interconnection line
34
is provided on the interlayer dielectric
20
to electrically connect the contact plugs
22
to each other. Thus, the first active region
16
a
is connected to the second active region
16
b
through the contact plugs
22
and the interconnection line
34
.
In the region B of
FIG. 1A
, an active region
16
c
doped with impurities is provided in the substrate
2
between field areas
6
. A first conductive line
10
a
and a second conductive line
10
b
are disposed at respective ones of the field areas
6
. While the conductive lines
10
a
and
10
b
are formed at the field areas
6
in
FIG. 1A
, the conductive lines
10
a
and/or
10
b
may become a gate electrode when crossing over the active region
16
c
. An interlayer dielectric
20
is provided on the substrate
2
including the conductive lines
10
a
and
10
b
. Contact plugs
24
are connected to the conductive lines
10
a
and
10
b
through the interlayer dielectric
20
. The contact plugs
24
are also connected to each other through the interconnection line
36
. Thus, the contact plugs
24
and the interconnection line
36
electrically connect the first conductive line
10
a
to the second connective line
10
b.
The region C of
FIG. 1A
illustrates a MOS-transistor having a gate structure and a source/drain region
18
on both sides of the gate structure. The gate structure includes a gate insulator
8
, a gate electrode
10
c
, and spacers
14
on sidewalls of the gate electrode
10
c
. The source/drain region
18
is provided by a lightly doped region
12
and a heavily doped region
16
d
. An interlayer dielectric
20
is provided on the substrate
2
having the MOS-transistor. And a contact plug
26
is also formed to electrically connect both the gate electrode
10
c
of the MOS-transistor and a doped active region
16
d
through the interlayer dielectric
20
. The contact plug
26
is connected to an interconnection line
38
.
As mentioned above, conventionally, otherwise electrically isolated regions are electrically connected to each other using contact plugs, such as the contact plugs
22
,
24
and
26
and interconnection lines, such as the interconnection lines
34
,
36
and
38
. The interlayer dielectric
20
is selectively etched to form a contact hole where the contact plugs
22
,
24
and
26
will be disposed. Processes for forming a hole pattern to provide contact plugs may become difficult as a semiconductor devices become more highly integrated.
In addition, as the semiconductor device becomes more highly integrated, processes for isolating adjacent patterns may become more difficult. For example, when a misalignment arises in a photolithography process for forming a contact hole on conductive lines
10
a
and
10
b
of the region B, an electrical short may occur between the active region
16
c
doped with impurities and the conductive lines
10
a
and/or
10
b
. To overcome this problem, the conductive lines
10
a
and
10
b
have been used as an ion implantation mask to provide self-alignment of the active region
16
c
. Thus, the active region
16
c
of the region B disposed between the field areas
6
is not doped with impurities if the conductive lines cross the region between the field areas
6
. Such a case is illustrated in FIG.
1
B. Where the conductive line
10
covers the region between the field areas
6
, an unwanted MOS-transistor may be formed that may degrade the performance of the device.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide an interconnection structure of a semiconductor device and methods of fabricating an interconnection structure. In particular embodiments of the present invention, a first active region and a second active region are provided in a substrate. A first field region in the substrate is disposed between the first active region and the second active region and an interlayer dielectric is provided on the substrate. A first unitary interconnection structure contacts and electrically connects the first active region and the second active region, the first unitary interconnection structure being disposed in the interlayer dielectric.
In further embodiments of the present invention, the first active region and the second active region have a surface substantially coplanar with a surface of the substrate. In such embodiments, the first unitary interconnection structure has a first surface that is substantially coplanar with the surface of the substrate and a second surface, opposite the first surface, that is substantially coplanar with a surface of the interlayer dielectric opposite the surface of the substrate.
In additional embodiments of the present invention, the interlayer dielectric includes an etch stop layer on the substrate, a first dielectric layer on the etch stop layer and a second dielectric layer on the first dielectric layer opposite the etch stop layer. Furthermore, the first dielectric layer and the second dielectric layer may have different etch rates with respect to each other.
The first unitary interconnection structure may be a material selected from the group including tungsten, aluminum, copper, titanium, titanium nitride and/or tantalum nitride.
In still further embodiments of the present invention, a third active region is provided in the substrate and second and third field areas in the substrate are provided on opposite sides of the third active region. A first conductive line is on the second field area and a second conductive line is on the third field area. A second unitary interconnection structure contacts the first conductive line and the second conductive line and electrically connects the first conductive line to the second conductive line. The second unitary interconnection structure is disposed in the interlayer dielectric. Furthermore, a portion of the interlayer dielectric is disposed on the third active region and in a gap between the first conductive line and the second conductive line.
In particular embodiments of the present invention, the first conductive line and the second conductive line each have a respective first surface opposite the substrate. The respective first surfaces of the first conductive line and the second conductive line are substantially coplanar. The first surfaces of the first conductive line and the second conductive line are not coplanar with the surface of the substrate. The second unitary interconnection s

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