Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-14
2004-10-05
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S365000, C257S369000
Reexamination Certificate
active
06800905
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly to an implanted asymmetric doped polysilicon-containing gate FinFET structure that is integrated with a thick polysilicon-containing gate. The present invention is also directed to a method to integrate the implanted asymmetric polysilicon-containing gate FinFET with a thick polysilicon-containing gate for manufacturing integration.
Over the past twenty-five years or so, the primary challenge of very large scale integration (VLSI) has been the integration of an ever-increasing number of metal oxide semiconductor field effect transistor (MOSFET) devices with high yield and reliability. This was achieved mainly in the prior art by scaling down the MOSFET channel length without excessive short-channel effects.
To scale down MOSFET channel lengths without excessive short-channel effects, gate oxide thickness is typically reduced while increasing channel-doping concentration. However, Yan, et al., “Scaling the Si MOSFET: From bulk to SOI to bulk”, IEEE Trans. Elect. Dev., Vol. 39, p. 1704, July 1992, have shown that to reduce short-channel effects for sub-0.05 Ã
m MOSFETs, it is important to have a backside-conducting layer present in the structure that screens the drain field away from the channel. The Yan, et al. results show that double-gated MOSFETs and MOSFETs with a top gate and a backside ground plane are more immune to short-channel effects and hence can be scaled to shorter dimensions than conventional MOSFETs.
The structure of a typical prior art double-gated MOSFET consists of a very thin vertical Si layer (fin) for the channel and the source/drain diffusions, with two gates, one on each vertical side of the channel. The term “Fin” is used herein to denote a semiconducting material which is employed as the body of the FET; the term “FinFET” refers to an FET with a fin body. The two gates are electrically connected so that they serve to modulate the channel. Short-channel effects are greatly suppressed in such a structure because the two gates very effectively terminate the drain field line preventing the drain potential from being felt at the source end of the channel. Consequently, the variation of the threshold voltage with drain voltage and with gate length of a prior art double-gated MOSFET is much smaller than that of a conventional single-gated structure of the same channel length.
One problem with prior art structures which comprise symmetric polysilicon gates on a FinFET is that the symmetric polysilicon gate FinFET structure will result in threshold voltages that are not compatible with existing CMOS circuit designs. For example, the NFET threshold voltage will be negative and the PFET will be quite positive. A potential solution to this problem is using a symmetric metal gate. Integration and processing difficulty has, however, made the development of a metal gate FinFET quite slow.
Another possible solution is an asymmetric doped polysilicon gate where one side of the Fin (i.e., thin film semiconducting layer) includes an N+ doped polysilicon gate and the other side of the Fin includes a P+ doped polysilicon gate. This asymmetry will shift threshold voltages to CMOS compatible levels in planar double-gate devices as well as FinFETs. However, in prior art asymmetric polysilicon gate structures thin polysilicon gates are employed. A problem with such structures is that thin polysilicon gates result in highly resistive gate electrodes. Additionally, the aspect ratio of the structures having thin gate electrodes makes the gate etch extremely difficult.
In view of the above-mentioned problems, there is a continued need for developing a new and improved FinFET structure in which the threshold voltage is compatible with current CMOS circuit designs and where low-resistance gate electrodes are realized.
BRIEF SUMMARY OF THE INVENTION
One object of the present invention is to provide a FinFET structure containing asymmetric polysilicon-containing gates which make the threshold voltage of the structure compatible with current CMOS circuit designs. The term “polysilicon-containing” is used herein to denote materials that are comprised of polySi or polySiGe.
Another object of the present invention is to provide an asymmetric FinFET structure wherein low-resistance gate electrodes are employed.
A still further object of the present invention is to provide an asymmetric FinFET structure in which the asymmetric polysilicon-containing gates are interconnected by an interconnect layer.
A yet further object of the present invention is to provide an asymmetric FinFET structure wherein a planarizing structure is present atop the asymmetric FinFET structure.
These and other objects and advantages are achieved in the present invention by providing a structure where an implanted asymmetric polysilicon-containing gate FinFET is integrated with a thick polysilicon-containing outer gate electrode (i.e., the planarizing structure). The integrated FinFET/thick polysilicon-containing gate structure allows for the production of a FinFET in which the threshold voltage is compatible with current CMOS circuit designs, and the resistivities of the gate electrodes are lower than conventional symmetric FinFETs.
One aspect of the present invention relates to a method of forming a plurality of conductive structures on a substrate. Specifically, the inventive method includes the steps of:
forming a first semiconductor structure of a first conductivity type, a second semiconductor structure of a second conductivity type, and a third semiconductor structure on a substrate, said third semiconductor structure being disposed between said first and second semiconductor structures and being separated therefrom by an insulator structure;
depositing an interconnect layer over at least said first, second and third semiconductor structures;
forming a planarizing conductor on said interconnect layer, said planarizing conductor having etch characteristics similar to those of said interconnect layer and said first and second semiconductor structures, but different from those of said insulator structure; and
patterning and etching said planarizing conductor, said interconnect layer, and said first and second semiconductor structures so that each has at least one lateral dimension that is substantially the same.
Another aspect of the present invention relates to an asymmetric field effect transistor (FET) which includes:
a p-type gate portion and an n-type gate portion on a vertical semiconductor body;
an interconnect between said p-type gate portion and said n-type gate portion; and a planarizing structure above said interconnect.
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Keunwoo Kim, et al., Optimal Double-Gate MOSFET's : Symmetrical or Asymmetrical Gates?, 1999 IEEE International SOI Conference, Oct. 1999, (pp. 98-99).
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Fried David M.
Nowak Edward J.
Rankin Jed H.
Canale Anthony
Fahmy Wael
Peralta Ginette
Scully Scott Murphy & Presser
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