Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2002-10-24
2004-11-02
Brock, II, Paul E (Department: 2815)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S124000, C438S127000
Reexamination Certificate
active
06812066
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a manufacturing method thereof and, more particularly, to a semiconductor device and a manufacturing method thereof which device provides a three-dimensional structure so as to increase a packaging density thereof.
As an electronic apparatus becomes smaller in size, weight and thickness, a semiconductor device used in such an electronic apparatus is required to be smaller in size and thickness. In an attempt to satisfy these requirements, the trend of a semiconductor device package has been shifting from a QFP (Quad Flat Package) for surface mounting in which package terminals are led out in four directions in the shape of a gull wing, to a BGA (Ball Grid Array) having external connection terminals arranged on the bottom of a package in the form of an area array, or to a CSP (Chip Size Package).
Among semiconductor packages like these, a package of a fan-out type is widely used, in which package a semiconductor chip is mounted on a wiring substrate (an interposer) and external connection terminals are arranged around the semiconductor chip by the interposer.
2. Description of the Related Art
FIG. 1
is a cross-sectional view of a conventional semiconductor device of the fan-out type. In
FIG. 1
, a semiconductor device
1
mainly comprises a substrate
2
, a semiconductor chip
4
, solder balls (bumps)
6
, and a sealing resin
8
. The substrate
2
, electrode patterns
10
and a bonding pad
12
compose an interposer. The interposer is used to electrically connect an external electrode and the semiconductor chip
4
.
The substrate
2
is formed of such a material as a polyimide resin, a ceramic resin, and a glass-epoxy resin. The substrate
2
has the semiconductor chip
4
mounted on a surface
2
a
thereof and also has the electrode patterns
10
formed on the surface
2
a
. The semiconductor chip
4
is fixed faceup on the substrate
2
by a DB material (a bonding pad)
5
. The electrode patterns
10
are provided by applying a copper film on the substrate
2
and forming the copper film into predetermined patterns by, for example, etching. The electrode patterns
10
are electrically connected to each other by wiring patterns not shown in the figures.
Some of the electrode patterns
10
are consolidated with the bonding pad
12
. The bonding pad
12
and an electrode of the semiconductor chip
4
are connected by a wire
14
. Thereby, the semiconductor chip
4
, the electrode patterns
10
and the bonding pad
12
are electrically connected via the wire
14
and the wiring patterns. The surface
2
a
of the substrate
2
is sealed by the sealing resin
8
formed of such a material as an epoxy resin so as to protect the semiconductor chip
4
, the wire
14
, the bonding pad
5
, and the other elements formed on the surface
2
a.
Further, a hole
16
penetrating through the substrate
2
is formed at a position facing each of the electrode patterns
10
. The hole
16
is formed by processing the substrate
2
by a laser, a drill or a metal mold, etc.
The solder balls
6
are arranged toward a back surface
2
b
of the substrate
2
. Each of the solder balls
6
is placed into the hole
16
, and is joined to the electrode pattern
10
through the hole
16
. That is, each of the solder balls
6
is fixed to the substrate
2
by being fixed to the electrode pattern
10
.
As described above, a package structure using an interposer in the semiconductor device
1
has been becoming a mainstream of a semiconductor device package. However, as a semiconductor device has been made to have an even higher density, a packaging area in a semiconductor package including a semiconductor chip has been becoming smaller. Accordingly, a package size of a semiconductor device is made smaller to the extent that a two-dimensional miniaturization of a package structure is supposedly reaching the limit. Therefore, to realize a further miniaturization of a semiconductor device, a three-dimensional (stack) packaging is required. As an example of the three-dimensional packaging, a semiconductor device having connection electrodes on the upper surface of a resin package is provided.
However, in order to provide connection electrodes on the upper surface of a resin package as mentioned above, wires have to be arranged around the resin package, making it difficult to provide the connection electrodes out on the upper surface of the resin package. For example, in a case where a wire connected to an external terminal formed on an interposer is led to the upper surface of the resin package after the formation thereof by being detoured around the outer surface of the semiconductor device so as to avoid the resin package, the wire becomes exposed and thus is likely to be cut, which impairs the reliability of the semiconductor device. Additionally, with this manner of arranging the connection electrodes, the wires become long so as to increase the impedance thereof, making it difficult for the semiconductor device to operate at high speed.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved and useful semiconductor device and a manufacturing method thereof in which device the above-mentioned problems are eliminated.
A more specific object of the present invention is to provide a semiconductor device and a manufacturing method thereof which device can be stacked on one another to form a semiconductor device package having a simple three-dimensional structure so as to increase a packaging density thereof.
In order to achieve the above-mentioned objects, there is provided according to one aspect of the present invention a semiconductor device comprising:
a first semiconductor element;
an external terminal used for an external connection;
an interposer having the first semiconductor element mounted on a first surface thereof and having the external terminal formed on a second surface thereof opposite to the first surface so as to electrically connect the first semiconductor element and the external terminal;
a resin sealing the first semiconductor element on the first surface; and
an interconnecting portion formed within the resin, the interconnecting portion having a first connecting part electrically connected to the external terminal and having a second connecting part exposed on an outer surface of the resin.
According to the present invention, the interconnecting portion electrically connects the external terminal and an external terminal of another semiconductor device of the same type contacting the second connecting part so that a plurality of the semiconductor devices of the same type can be stacked. That is, the interconnecting portion enables stacking and combining a plurality of the semiconductor devices effectively so as to increase a packaging density of a three-dimensional structure thereof. In addition, wires (including the interconnecting portion) are formed in the resin so as to achieve the shortest wiring, providing a semiconductor device having a simple package structure.
In order to achieve the above-mentioned objects, there is also provided according to another aspect of the present invention a semiconductor device comprising:
a semiconductor element;
an external terminal used for an external connection;
an interposer having the semiconductor element mounted on a first surface thereof and having the external terminal formed on a second surface thereof opposite to the first surface so as to electrically connect the semiconductor element and the external terminal;
a resin sealing the semiconductor element on the first surface; and
an interconnecting portion formed on a surface of the semiconductor element within the resin, the interconnecting portion having a first connecting part electrically connected to the semiconductor element and having a second connecting part exposed on an outer surface of the resin.
According to the present invention, the interconnecting portion is formed on the surface of the semiconductor element wit
Takashima Akira
Taniguchi Fumihiko
Brock II Paul E
Fujitsu Limited
Westerman Hattori Daniels & Adrian LLP
LandOfFree
Semiconductor device having an interconnecting post formed... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having an interconnecting post formed..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having an interconnecting post formed... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3322190