Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1998-01-16
2004-12-21
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S488000, C438S584000, C257S377000, C257S408000, C257S411000
Reexamination Certificate
active
06833293
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a buried conductive layer which is connected to a source/drain of MOS transistor and extends over a gate electrode of the MOS transistor and a method for manufacturing the same.
2. Description of the Related Art
In recent years, as high integration and scale down (shrink) of a semiconductor device have progressed, the alignment margin in the photolithography process for a contact hole which is formed in order to connect a source/drain of a MOS transistor and a wiring layer to each other is being decreased. In addition, the aspect ratio of the contact hole is also being increased. Now, the aspect ratio is defined by the ratio of a depth to a diameter of the contact hole. From the foregoing, the technique is adopted in which the source/drain of the MOS transistor and the wiring layer are not directly connected each other, but are indirectly connected to each other through a buried layer (an extraction electrode) formed on the source/drain.
Now, the process of manufacturing a MOS transistor employing that baried conductive layer will hereinbelow be described simply with reference to
FIGS. 1A
to
1
E.
Firstly, as shown in
FIG. 1A
, after a field oxide film
102
has been formed in a region to be an isolation region of a silicon substrate
101
by utilizing the well known LOCOS (Local Oxidation of Silicon) method, a gate oxide film
103
is formed in an active region surrounded by the field oxide film
102
by the thermal oxidation method. Thereafter, a polycrystalline silicon containing phosphorus or arsenic and a silicon oxide film
104
are formed in this order by the CVD method, and those films are then subjected to the anisotropic etching with a photo resist film (not shown), which was formed so as to have a gate electrode pattern by the photolithography technology, as an etching mask, thereby forming a gate electrode
105
formed of that polycrystalline silicon film. In addition, the impurity ions are implanted into the unmasked region with the gate electrode
105
as a mask, thereby forming a pair of lightly doped impurity diffusion layers
106
in surface portions of the silicon substrate
101
on the both sides of the gate electrode.
Next, as shown in
FIG. 1B
, after a silicon oxide film has been formed on the whole surface of the substrate
101
, the silicon oxide film is selectively etched away by the anisotropic etching, thereby forming a side wall oxide film
107
on each of both side faces of the gate electrode
105
and the silicon oxide film
104
by the anisotropic etching. Incidentally, a portion of the gate oxide film
103
formed on the region which is not covered with the gate electrode
105
or the side wall oxide film
107
is removed concurrently with the selective etching of that silicon oxide film.
Nest, as shown in
FIG. 1C
, a polycrystalline silicon film
108
containing phosphorus or arsenic is formed on the whole surface of the silicon substrate
101
by the CVD method. This polycrystalline silicon film
108
will become a buried conductive layer later. Thereafter, the impurity ions are implanted into the unmasked region with both the gate electrode
105
and the side wall oxide film
107
as a mask, thereby forming a pair of highly doped impurity diffusion layers
109
as a source and a drain in the surface regions of the silicon substrate
101
on the both sides of the gate electrode
105
.
Next, as shown in
FIG. 1D
, after a photo resist film
110
has been applied to the polycrystalline silicon film
108
, the photo resist film
110
is processed so as to have a pattern, of the buried conductive layer, having a slit
110
a
on the gate electrode
105
by the photolithography method. Thereafter, the polycrystalline silicon film
108
is selectively etched away by the anisotropic dray etching with the photo resist film
110
as an etching mask, thereby processing the polycrystalline silicon film
108
so as to have a pattern which is separated into portions, located on the both sides of the gate electrode
105
, with a width of the slit
110
a.
Next, as shown in
FIG. 1E
, the photo resist film
110
is removed. By carrying out the above-mentioned process, it is possible to form buried conductive layers
111
, formed of the polycrystalline silicon film
108
, which are respectively self-aligned with the pair of impurity diffusion layers
109
of the MOS transistor and each of which extends up to a upper portion of the gate electrode
105
.
The buried conductive layers
111
are formed in such a way, whereby the alignment margin of the contact hole for the wiring connection which is formed through the insulating film on the associated buried conductive layer
111
can be increased and also the substantial aspect ratio of that contact hole can be decreased by a thickness of the associated buried conductive layer
111
. As a result, it is possible to improve the reliability of the wiring connection in the contact hole portion. In addition, since the impurity diffusion layers
109
each having a shallower junction can also be formed, while suppressing occurrence of any crystal defect in the silicon substrate
101
, by the thermal diffusion from the buried conductive layers
111
, formation of the buried conductive layer
111
is also suitable for scale down of the semiconductor device.
Now, when forming the above-mentioned buried conductive layer
111
, in the process shown in
FIG. 1D
, the slit
110
a
of the photo resist film
110
needs to be formed so as to reach the portion above the upper side of the gate electrode
105
, and also a width thereof needs to be made much smaller than a width of the gate electrode
105
(a gate length).
This reason is that if due to the mismatch of alignment in the photolithography process, the central position of the slit of the photo resist film
110
is shifted in the direction of a width of the gate electrode by a distance X as shown in
FIG. 2
for example so that the edge of the hole of the photo resist film
110
is located on the associated side wall oxide film
107
, and under this condition, the polycrystalline silicon film
108
is subjected to the anisotropic etching, then not only the buried conductive layer
111
in the boundary portion between the buried conductive layer
111
of interest and the associated side wall oxide film
107
will be selectively etched away during the over-etching, but also the thin portion of the side wall oxide film
107
as well as the gate oxide film
103
will be etched away, and finally the surface of the silicon substrate
101
will be exposed.
Then, if the surface of the silicon substrate
101
is exposed, since the etch selectivity of the silicon substrate
101
to the buried conductive layer
111
formed of a polycrystalline silicon film is remarkably small, even the surface of the silicon substrate
101
will be partially etched away, and as a result, a trench
120
will be formed in the silicon substrate
101
by the etching. In such a way, the silicon substrate
101
will be damaged. Such damage of the silicon substrate
101
results in the performance of the MOS transistor being remarkably degraded.
In order to avoid that situation, the width of the slit
110
a
of the photo resist film
110
needs to be made much smaller than the gate length of the gate electrode
105
so as for the hole edge of the photo resist film
110
not be located on the associated side wall oxide film
107
even if the slight mismatch of alignment occurs. In other words, this means that the gate length of the gate electrode
105
needs to be made much larger than the width of the slit
110
a
of the photo resist film
110
. Thus, even if the width of the slit
110
a
of the photo resist film
110
should be made a minimum processing size provided by the photolithography technology, the gate length of the gate electrode
105
needs to be made much larger than the minimu
Connolly Bove Lodge & Hutz
Hume Larry J.
Pham Long
Rao Shrinivas
United Microelectronics Corporation
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