Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-03-06
2004-02-17
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C712S244000
Reexamination Certificate
active
06694457
ABSTRACT:
THE FIELD OF THE INVENTION
The present invention relates to monitoring the execution of privileged instructions in computer systems, and more particularly to monitoring the execution of privileged instructions in computer systems using hardware single-stepping.
BACKGROUND OF THE INVENTION
Computer systems include at least one processor and memory. The memory stores application program instructions, data, and an operating system. The operating system controls the processor and the memory for system operations and for executing the application program instructions. Processors often have a current privilege level which controls the application instruction execution in the computer system by controlling accessibility to system resources, such as system registers, system instructions, and system memory pages. The current privilege level varies between two or more execution privilege levels.
Sometimes it is desirable to run as an unprivileged application a program that was originally intended to run as a privileged application. Such an application is referred to herein as a privilege desiring application. It would be desirable to monitor, count and trace the execution of privileged instructions in a privilege desiring application. One current solution for monitoring the execution of instructions in a program is to build a software emulator to handle faulting instructions so that execution can continue when a fault occurs. However, this solution is very complex, and requires software to be developed that can update the processor state as if a faulting instruction had been executed.
Software debuggers have also been developed to monitor the execution of program instructions. Software debuggers typically make use of a single-step feature. A single-step feature may be implemented in software, or may be a hardware feature provided by the processor. A single-step feature has been used by software debuggers to step through a program one instruction at a time, monitor how the processor state changes after each instruction, and identify errors based on the changes in the processor state. A hardware single-step feature has not previously been used as part of a solution for monitoring, counting, and tracing the execution of privileged instructions in a privilege desiring application.
It would be desirable to provide a simplified solution for monitoring, counting and tracing the execution of privileged instructions in a privilege desiring application, without the requirement of building a complex software emulator.
SUMMARY OF THE INVENTION
The present invention provides a computer system and method for monitoring the execution of privileged instructions by a processor of a computer system. The processor includes a current privilege level. The processor automatically generates a fault when attempting execution of an instruction requiring a higher privilege level than the current privilege level of the processor. The current privilege level of the processor is raised in response to a fault generated by a first faulting instruction. The first faulting instruction is executed. A trap is generated by executing the first faulting instruction. The current privilege level of the processor is lowered in response to the trap.
In one embodiment, the current privilege level of the processor is lowered before executing the instructions.
In one embodiment, a fault handler is invoked to process the fault. The step of raising the current privilege level is performed by the fault handler.
In one embodiment, a trap handler is invoked to process the trap. The step of lowering the current privilege level is performed by the trap handler.
In one embodiment, a single-step mode of the processor is enabled in response to the fault. The single-step mode is enabled by setting a field in a system register of the processor.
In one embodiment, state information is stored in response to the fault. The state information includes the number of instructions that caused a fault and an identification of instructions that caused a fault.
One form of the present invention provides a method of executing instructions by a processor of a computer system controlled by an operating system. The processor has a current privilege level. A privileged operation fault is generated based on the attempted execution of a first instruction. The current privilege level of the processor is raised in response to the privileged operation fault. A single-step mode is enabled in response to the privileged operation fault. The first instruction is executed, thereby generating a single-step trap. The current privilege level of the processor is lowered in response to the single-step trap. The single-step mode is disabled in response to the single-step trap.
One form of the present invention provides a computer system including a processor having a current privilege level that controls application instruction execution in the computer system. A memory stores a privilege desiring application program having application instructions. An operating system stored in the memory controls the processor. The operating system includes a fault handler and a trap handler. The fault handler raises the current privilege level and enables a single-step mode in response to a privileged operation fault. The trap handler lowers the current privilege level and disables the single-step mode in response to a single-step trap.
One form of the present invention provides a computer readable medium containing an operating system for controlling a processor of a computer system to perform a method of monitoring the execution of privileged instructions. The processor has a current privilege level that controls instruction execution in the computer system. The method includes raising the current privilege level of the processor in response to a fault generated by a first faulting instruction. The first faulting instruction is executed. A trap is generated by executing the first faulting instruction. The current privilege level of the processor is lowered in response to the trap.
The present invention provides a simplified solution for monitoring, counting and tracing the execution of privileged instructions in a privilege desiring application program. In one embodiment, a hardware single-step feature of a processor is used to temporarily grant privileges to particular instructions. Privileged instructions are “emulated” by the hardware itself, eliminating the need for building a complex software emulator.
REFERENCES:
patent: 4809160 (1989-02-01), Mahon et al.
patent: 5134701 (1992-07-01), Mueller et al.
patent: 5201043 (1993-04-01), Crawford et al.
patent: 5371879 (1994-12-01), Schiffleger
patent: 5450586 (1995-09-01), Kuzara et al.
patent: 5465335 (1995-11-01), Anderson
patent: 5596717 (1997-01-01), Marshall, Jr.
patent: 5742755 (1998-04-01), Hervin
patent: 5815702 (1998-09-01), Kannan et al.
patent: 5859991 (1999-01-01), Narayan
patent: 5889978 (1999-03-01), Jayakumar
patent: 5915114 (1999-06-01), McKee et al.
patent: 6199181 (2001-03-01), Rechef et al.
patent: 6240531 (2001-05-01), Spilo et al.
patent: 6397242 (2002-05-01), Devine et al.
patent: 6516395 (2003-02-01), Christie
Hewlett-Packard Product Manual, “Overview of IA-64 Architecture”.
Hewlett-Packard Product Manual, “IA-64 Software Conventions and Runtime Architecture”, Version 1.0 (Aug. 31, 1999).
Intel Product Manual, “Intel IA-64 Architecture Software Developer's Manual”, vol. 1: IA-64 Application Architecture, Revision 1:1 (Jul. 2000).
Intel Product Manual, “Intel IA-64 Architecture Software Developer's Manual”, vol. 2: IA-64 System Architecture, Revision 1.1 (Jul. 2000).
Intel Product Manual, “Intel IA-64 Architecture Software Developer's Manual”, vol. 3: IA-64 Instruction Set Reference, Revision 1.1 (Jul. 2000).
Intel Product Manual, “Intel IA-64 Architecture Software Developer's Manual”, vol. 4: Itanium Processor Programmer Guide, Revision 1.1 (Jul. 2000).
Intel Product Manual, “Intel IA-64 Architecture Software Developer's Manual”, Itanium Processor Microarchitecture Reference for Software
Hewlett--Packard Development Company, L.P.
Iqbal Nadeem
LandOfFree
System and method for monitoring execution of privileged... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for monitoring execution of privileged..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for monitoring execution of privileged... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3320882