Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-26
2004-06-22
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000
Reexamination Certificate
active
06753560
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory composed of an MFMIS transistor including a ferroelectric capacitor formed on or above a field effect transistor and a method for driving the semiconductor memory.
An MFMIS transistor including a ferroelectric capacitor formed on or above a field effect transistor has a Metal/Ferroelectric/Metal/Insulator/Semiconductor multi-layer structure. The MFMIS transistor is formed in either of the following two known structures: In the first structure, as shown in
FIG. 5A
, the MFMIS transistor includes dopant diffusion layers
101
serving as a source and a drain formed in surface portions of a semiconductor substrate
100
, and a floating gate
103
, a ferroelectric film
104
and a control gate
105
successively formed above the semiconductor substrate
100
with a gate insulating film
102
sandwiched therebetween, namely, the gate electrode of the field effect transistor also works as the lower electrode of the ferroelectric capacitor; and in the second structure, as shown in
FIG. 5B
, the MFMIS transistor includes dopant diffusion layers
111
serving as a source and a drain formed in surface portions of a semiconductor substrate
110
, a gate electrode
113
formed above the semiconductor substrate
110
with a gate insulating film
112
sandwiched therebetween, a floating gate
116
formed in an interlayer insulating film
114
covering the gate electrode
113
and connected to the gate electrode
113
through a contact plug
115
, a ferroelectric film
117
formed on the floating gate
116
and a control gate
118
formed on the ferroelectric film
117
, namely, the gate electrode of the field effect transistor is electrically connected to the lower electrode of the ferroelectric capacitor.
Now, a data erase operation, a data write operation and a data read operation of a conventional semiconductor memory including the MFMIS transistor will be described.
First, in the data erase operation, negative potential is applied to the semiconductor substrate, so as to apply a voltage between the control gate of the MFMIS transistor and the semiconductor substrate. Thus, polarization of ferroelectric films of the MFMIS transistors of all memory cells is turned along one direction, thereby erasing data stored in all the memory cells.
Next, in the data write operation, a voltage is applied between the substrate and the control gate of the MFMIS transistor of a memory cell disposed at an address selected by a writing transistor, so as to reverse the polarization direction of the ferroelectric film of this transistor (to place it in an on-state) or the polarization direction of the ferroelectric film of the transistor is kept (to place it in an off-state) without applying the voltage between the control gate and the substrate. Specifically, a data is written by causing either of two kinds of polarized states, that is, to reverse the polarization (which corresponds to an on-state) and to keep the polarization (which corresponds to an off-state), in accordance with the input data. Since the polarized state of the ferroelectric film is kept without applying a voltage, the memory cell functions as a nonvolatile semiconductor memory.
In the data read operation, a reading transistor is turned on, so as to detect voltage drop accompanied by a current flowing through the channel region of the field effect transistor included in the MFMIS transistor to a ground line (namely, a drain-source current). Since the channel resistance is varied depending upon the polarized state of the ferroelectric film of the MFMIS transistor, a data written in the MFMIS transistor can be thus read.
Since the ferroelectric capacitor (with capacitance C
f
) and the capacitor (with capacitance C
g
) of the field effect transistor are serially connected to each other in the MFMIS transistor, a voltage applied to the ferroelectric capacitor is merely a part of the voltage applied between the control gate and the semiconductor substrate, which corresponds to a voltage obtained by dividing the applied voltage by the reciprocal of the capacitance.
Therefore, in order to reverse the polarization of the ferroelectric film to write a data (in a data program), a voltage (C
f
+C
g
)/C
g
times as large as a voltage necessary for reversing the polarization of the ferroelectric film (namely, polarization reversing voltage) should be applied between the control gate and the semiconductor substrate. Therefore, a voltage necessary for data write is unavoidably high.
As a countermeasure, Japanese Laid-Open Patent Publication No. 8-97386 describes that a voltage applying transistor is connected to the floating gate of the MFMIS transistor so as to externally apply a writing voltage through the voltage applying transistor to the floating gate.
Since a voltage can be thus independently applied between the control gate and the floating gate, the voltage necessary for data write can be lowered.
The structure described in Japanese Laid-Open Patent Publication No. 8-97386 requires, however, two systems of voltage supply means, namely, one including a voltage supply and a voltage supply line for supplying a voltage to the control gate and the other including a voltage supply and a voltage supply line for supplying a voltage to the floating gate. Therefore, there arises another problem that the circuit configuration is so complicated that the structure of the entire semiconductor memory becomes complicated.
SUMMARY OF THE INVENTION
In consideration of the aforementioned conventional problems, an object of the invention is lowering a voltage necessary for data write with a simple structure.
In order to achieve the object, the semiconductor memory of this invention comprises an MFMIS transistor including a first field effect transistor and a ferroelectric capacitor formed on or above the first field effect transistor with a gate electrode of the first field effect transistor working as or being electrically connected to a lower electrode of the ferroelectric capacitor, an upper electrode of the ferroelectric capacitor working as a control gate and the first field effect transistor having a first well region; and a second field effect transistor having a second well region that is isolated from the first well region of the first field effect transistor, and the first well region of the first field effect transistor is electrically connected to a source region of the second field effect transistor, and the gate electrode of the first field effect transistor is electrically connected to a drain region of the second field effect transistor.
In the semiconductor memory of this invention, the first well region of the first field effect transistor is electrically connected to the source region of the second field effect transistor, and the gate electrode of the first field effect transistor is electrically connected to the drain region of the second field effect transistor. Therefore, the first well region and the gate electrode of the first field effect transistor are connected to each other through the source region and the drain region of the second field effect transistor. As a result, when the second field effect transistor is in an on-state, the first well region and the gate electrode of the first field effect transistor are short-circuited.
Accordingly, when the first well region and the gate electrode of the first field effect transistor are short-circuited by turning on the second field effect transistor in writing a data in the MFMIS transistor, a voltage applied between the control gate and the first well region of the MFMIS transistor can be sufficiently equal to a voltage for reversing polarization of the ferroelectric film of the ferroelectric capacitor.
In this manner, a voltage necessary for data write can be lowered in the semiconductor memory of this invention with a simple structure.
In the semiconductor memory, the first field effect transistor, the second field effect transistor and a driving circuit for driving the first and second field effe
Kato Yoshihisa
Shimada Yasuhiro
Flynn Nathan J.
Matsushita Electric - Industrial Co., Ltd.
Quinto Kevin
LandOfFree
Semiconductor memory and method for driving the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory and method for driving the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory and method for driving the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3320659