Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1994-02-09
2004-06-22
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S066000, C257S408000
Reexamination Certificate
active
06753576
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuit processing, and more specifically to a method of forming a one-sided polysilicon thin film transistor.
BACKGROUND OF THE INVENTION
The basic SRAM cell can be formed using cross-coupled CMOS inverters having 2 each n-channel and p-channel transistors. The cell is accessed by, typically, 2 n-channel control gates for a standard SRAM cell and 4 control gates for 2-port memory devices. To conserve physical layout space, the p-channel transistors are often replaced with resistive loads.
Use of the p-channel transistors as the load devices for the SRAM cell, however, results in the cell having better electrical characteristics. Such cells are faster than those using resistive loads, since the p-channel transistors provide a higher drive current than high resistance devices. Also, use of p-channel transistors gives higher immunity to soft errors, such as those caused by alpha particle impacts and noise. The primary disadvantage of SRAM cells incorporating p-channel load transistors is that the layout area for each cell is significantly larger than those using resistive loads. This reduces device density and increases chip costs.
Bottom-gated polysilicon PMOS transistors, or an inverted form of the transistors, are often used as the p-channel transistors or load devices in the SRAM cell. Stacking the p-channel transistors over the n-channel transistors increases device density. Today, the polysilicon PMOS transistors are used, for example, as the load devices in four megabit SRAM cells to improve the stability of the cell and reduce the cell's stand-by current. These load devices, generally termed thin film transistors, may be built in 10 to 100 nanometers of polysilicon deposited on top of an oxide layer. In most applications, the gate of the thin film transistor is shielded at the bottom of the transistor body by a layer of oxide as shown in the prior art FIG.
1
. After the gate
50
formation, a gate oxide layer is formed over the gate thus encapsulating the gate. A thin film of polysilicon
52
is deposited covering the gate. The thin film of polysilicon is appropriately doped to form an n-type channel region above the gate and p
+
source and drain regions adjacent to the n-type channel region and above the gate.
The typical bottom-gated thin film transistor, however, has a high grain-junction leakage current. The presence of grain boundary traps between, for example, the p
+
drain region and the n-type channel region causes field-enhanced generation current. This field enhanced current causes the leakage or off-state current of the cell to be high.
Several methods have been proposed to control the field-enhanced current in the bottom-gated polysilicon thin film transistor. See, for example, A Polysilicon Transistor Technology for Large Capacity SRAMs, by Ikeda et al, IEDM 469-472, 1990 and A 59 um
2
Super Low Power SRAM Cell Using a New Phase-Shift Lithography, by T. Yamanaka et al, IEDM 477-480, 1990. A gate to drain off-set structure of the polysilicon PMOS transistor is proposed whereby the leakage current and the stand-by dissipation power required for the memory cell are reduced to more acceptable levels.
As shown in prior art
FIG. 2
, the heavily doped p
+
drain region
54
is offset from the transistor gate
50
. However, the lightly doped n-type channel region which extends further over the transistor gate has the same doping concentration as the gate which results in some additional current loss. It would therefore be desirable to provide an improved off-set structure which reduces the drain electric field without compromising the drive current. It would further be desirable to form the improved structure utilizing current fabrication techniques easily adapted for use with standard integrated circuit process flows.
SUMMARY OF THE INVENTION
The invention may be incorporated into a method for forming a semiconductor device structure, and the semiconductor device structure formed thereby, by forming a first conductive structure over a portion of the integrated circuit. A first dielectric layer is formed over the first conductive structure. A polysilicon layer, having a first and a second end, is formed over the first dielectric layer. A channel region is formed in the polysilicon layer substantially over the first conductive structure. A source region is formed in the polysilicon layer adjacent to the first end of the channel region. A LDD region is formed in the polysilicon layer adjacent to the second end of the channel region. A drain region is formed in the polysilicon layer adjacent to the LDD region.
REFERENCES:
patent: 4581623 (1986-04-01), Wang
patent: 4686758 (1987-08-01), Liu et al.
patent: 4952825 (1990-08-01), Yoshida
patent: 5112764 (1992-05-01), Mitra et al.
patent: 5198379 (1993-03-01), Adan
patent: 5262655 (1993-11-01), Ashida
patent: 7132365 (1982-08-01), None
patent: 3260162 (1988-10-01), None
patent: 0214172 (1989-08-01), None
patent: 0260857 (1989-10-01), None
patent: 0023669 (1990-01-01), None
patent: 0094478 (1990-04-01), None
patent: 0197173 (1990-08-01), None
Wolf et al., Silicon Processing for the VLSI Era, vol. 1—Process Technology, 1986, Lattice Press, pp. 308-309.*
Fichtner, et al., “Experimental results in submicron-Size P-Channel MOSFET's”, IEEE Electron Device Letters, vol. EDL-3, No. 2, Feb. 1982.*
Article entitled “A Polysilicon Transistor Technology for Large Capacity SRAMs” by S. Ikeda et al, IEDM 90, pp. 469-472, 1990.
Article entitled “A 5.9 um2Super Low Power SRAM Cell Using a New Phase-Shift Lightography” by T. Yamanaka et al, IEDM 90, pp. 477-480, 1990.
Ohkubo et al., “16Mbit SRAM Cell Technologies for 2.OV Operation”, 1991 IEEE, IEDM pp. 91-481-91-484.
Liu et al., “Inverted Thin-Film Transistors with a Simple Self-Aligned Lightly Doped Drain Structure”, IEEE Transactions on Electron Devices, Vo. 39, No. 12, Dec. 1992.
Liu et al., “High Reliability and High Performance 0.35 &mgr;m Gate-Inverted TFT's for 16Mbit SRAM Applications Using Self-Aligned LDD Structures”, 1992 IEEE, IEDM 92-823-92-826.
Hayashi et al., “A High Performance Polysilicon TFT Using RTA and Plasma Hydrogenation Applicable to Highly Stable SRAMs of 16Mbit and Beyond”, 1992 Symposium on VLSI Technology Digest of Technical Papers, 1992 IEEE, pp. 36-37.
Eckert George
Jorgenson Lisa K.
Munck William A.
STMicroelectronics Inc.
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