Method of forming adjacent holes on a semiconductor substrate

Details Method of forming adjacent holes on a semiconductor substrate Method of forming adjacent holes on a semiconductor substrate

2003-09-16

2004-12-28

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S638000, C438S639000

Reexamination Certificate

active

06835653

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates to a method of forming a plurality of holes on a semiconductor substrate, and more particularly, to a method of forming two adjacent holes with a fine line structure between the adjacent holes on a semiconductor substrate.
2. Description of the Prior Art
With the development of modern technology, semiconductor products have applied more widely in each field of life, especially in the fields of communication and electric products. Since high technology products have been pushed for size reductions, integrations of semiconductor products have to be raised. Therefore each unit area of the substrate comprises more semiconductor elements, and the spacing between the semiconductor elements becomes smaller and smaller. However, there are many problems resulting from the high integration requirement. For example, more than one photomask and photo-etch-process (PEP) are needed to perform complicated processes to define the pattern of an original circuit design when fabricating metal lines with a small width or holes with a small size. Forming opening structures, such as contact holes, is a basic process of fabricating semiconductor products. In order to match the high-integration requirement, an original circuit design may comprise two adjacent holes that are too close to be fabricated on the substrate so as to produce failed pattern or to cause material damaged.
Please refer to
FIGS. 1-3
.
FIGS. 1-3
are schematic diagrams of a fabrication process of forming two adjacent holes on a semiconductor substrate
10
according to the prior art. The semiconductor substrate
10
comprises a plurality of gates
12
,
14
,
16
,
18
, a passivation layer
24
, a borophos-phosilicate glass (BPSG) layer
20
serving as an insulating layer, and an undoped silicate glass (USG) layer
22
. At first, a photoresist layer (not shown) is formed on the USG layer. Then a PEP is performed to remove portions of the photoresist layer at locations where the two adjacent holes are predetermined formed so as to form a patterned photoresist layer
26
. Referring to
FIG. 2
, an anisotropic etching process, such as a dry-etching process, is performed to remove portions of the USG layer
22
and the BPSG layer
20
not covered by the patterned photoresist layer
26
to expose the passivation layer
24
so as to form two adjacent holes
28
,
30
. Finally, as shown in
FIG. 3
, the patterned photoresist layer
26
is removed.
Since the holes
28
and
30
are very close, there is a fine line structure
32
with a very small width formed by the USG layer
22
and the BPSG layer
20
between the holes
28
and
30
. For example, the width of the fine line structure
32
may be smaller than 100 angstroms (Å). In this condition, if only one photomask is used to transfer the original circuit design to the photoresist layer, it is hard to define the pattern of the fine line structure
32
accurately on the photoresist layer to form an ideal patterned photoresist layer
26
. In contrast, after the photolithography process, the pattern of the fine line structure
32
may be transferred on a shifting location or to have a changed width, and even more the fine line structure
32
may disappear. Those defects seriously affect following processes and the yield of products. For example, if the fine line structure
32
has to be formed between the gates
14
and
16
according to the original circuit design, the following formed materials, such as a conductive material, doped polysilicon, on the fine line structure
32
will shift together when the patterned photoresist layer
26
can not define the fine line structure
32
in a correct location, which results in a disorder of circuits on the semiconductor substrate, such as short or failed electrical connection. Furthermore, the photoresist layer for transferring the photomask pattern needs to have a greater thickness in the prior art. As a result, a higher aspect ratio of the photoresist layer
26
appears after the PEP. Thus the photoresist layer
26
easily collapses during another fabricating process to cause serious problems.
Please refer to
FIGS. 4-5
.
FIGS. 4-5
are schematic diagrams of the fabrication of forming adjacent holes by using a hard mask according to the prior art. The semiconductor substrate
50
comprises a plurality of gates
52
,
54
,
56
,
58
, a passivation layer
60
covering the gates
52
,
54
,
56
,
58
, a BPSG layer
62
, and a USG layer
64
. As shown in
FIG. 4
, a hard mask
66
formed by silicon nitride is deposited on the USG layer
64
, and a photoresist layer
68
is deposited on the hard mask
66
. A photolithography process is then performed to transfer the photomask pattern to the photoresist layer and form a patterned photoresist layer
68
. As shown in
FIG. 5
, an etching process is performed to remove the hard mask
66
not covered by the patterned photoresist layer
68
so that the remaining hard mask
66
has a pattern the same as the patterned photoresist layer
68
. And then the patterned photoresist layer
68
is removed. An etching process is next performed to remove the USG layer
64
and the BPSG layer
62
not covered by the hard mask
66
to expose portions of the surface of the passivation layer
60
. Finally, the hard mask
66
is removed or remained according to process design to form the two adjacent holes
70
and
72
and the fine line structure
74
.
In this prior art, although a patterned photoresist layer with high aspect ratio is not needed during the etching process of the USG layer
64
and the BPSG layer
62
, the problem of inaccurately transferring the pattern of the fine line structure
74
still exists because the fine line structure
74
has a very small width, which reduces the yield of the semiconductor products.
SUMMARY OF INVENTION
It is therefore a primary objective of the claimed invention to provide a method for forming adjacent holes by transferring patterns accurately so as to solve the above-mentioned problem.
According to the claimed invention, a method for forming two adjacent holes on a semiconductor substrate is disclosed, wherein the two adjacent holes are a first hole and a second hole separated by a fine line structure. The method comprises providing a semiconductor substrate with an insulating layer on its surface and forming a step-shaped structure on the surface of the insulating layer, wherein the step-shaped structure includes a first horizontal surface, a second horizontal surface, and a vertical surface between the first and the second horizontal surfaces. The method further comprises depositing a sacrificial layer with an average thickness on the insulating layer to cover the first horizontal surface, the second horizontal surface, and the vertical surface, forming a patterned photoresist layer covering portions of the first and the second horizontal surface, performing an etch-back process to remove a portion of the sacrificial layer that is on the first and the second horizontal surface and not covered by the patterned photoresist layer to form a spacer on the vertical surface, removing the patterned photoresist layer, and finally taking the spacer and the remaining sacrificial layer as a hard mask to etch the insulating layer not covered by the hard mask so as to form the adjacent first hole and second hole.
It is an advantage of the claimed invention that the method uses two photolithography processes (with two patterned photoresist layers) and a sacrificial layer serving as a hard mask for transferring the original circuit design and photomask pattern, so that the photomask pattern can be transferred more accurately and the transformation failure from exceeding an exposure limit in the prior art can be avoided. According to the claimed invention, after the second etching process is performed, a well-known technology can be used to adjust a bottom width of the spacer on the surface of the vertical surface when the sacrificial layer is etched back so as to gain a very small dimension of the fine

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