Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-09
2004-02-24
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S356000, C257S409000
Reexamination Certificate
active
06696734
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the device, particularly to technique improving operation sustaining voltage characteristic of high sustaining voltage MOS transistor for high voltage of power source (HV-VDD) used for an LCD driver, an EL driver and so on.
2. Description of the Related Art
A semiconductor device according to the related art will be described below referring a section view of an LDD type high sustaining voltage MOS transistor shown in FIG.
12
.
In
FIG. 12
, a gate electrode
53
is formed on a P type semiconductor substrate (P-Sub)
51
through a gate insulation film
52
. An N+ type source region
54
is formed so as to be adjacent to one end of said gate electrode
53
, an N− type drain region
56
is formed facing said source region
54
through a channel region and further separated from the other end of the gate electrode
53
, and an N+ type drain region
57
is formed so as to be included in an N− type drain region
56
.
In the prior art, a low concentration N− type drain region
56
is formed by thermal diffusion of about 1000° C. to 1100° C. so as to form a gentle slope and a deep diffusion layer.
However, even with such the construction, voltage between source and drain (BVDS: sustaining voltage at OFF) is high, but sustaining voltage (VSUS: sustaining voltage at ON) being operation sustaining voltage of the voltage is about 30 V at most in the prior art.
A mechanism decreasing the above-mentioned operation sustaining voltage will be described below.
In such the N channel type high sustaining voltage MOS transistor, a horizontal bipolar transistor
60
having the drain region
57
as corrector (N+), the source region
54
as emitter (N+), and the semiconductor substrate
51
as base (P) is formed parasitically as shown in FIG.
13
and FIG.
14
. Decreasing of operation sustaining voltage VSUS even if voltage between source and drain BVDS being sustaining voltage at OFF is caused by ON of the parasitical bipolar transistor
60
. Thus, operation range of the N channel type high sustaining voltage MOS transistor is limited and operation at all over the range is difficult.
An operation of said bipolar transistor
60
will be described below.
AS shown in
FIG. 13
, gate voltage (VG)(>Vt: threshold voltage) is added to the gate electrode
53
, voltage of a drain electrode (VD) (>>VG) contacting the drain region
57
is added, and a positive feedback loop described later (refer
FIG. 15
) is formed in the case of ON of the MOS transistor.
That is, {circle around (1)} avalanche multiplication generates in a depletion layer by electron of a channel region
62
accelerated at a depletion layer near the drain region
57
so as to generate a pair of an electron and a hole. {circle around (2)} Said hole flows in the substrate (substrate current: ISub) {circle around (3)} Said substrate current (ISub) generates voltage slope in the semiconductor substrate
51
to raise substrate voltage. {circle around (4)} Junction between the source region
54
and the substrate
51
is biased to forward direction. {circle around (5)} Electron is implanted from the source region
54
to the substrate
51
. {circle around (6)} The implanted electron reaches he drain region
57
and further occurs avalanche multiplication.
Thus, by forming the positive feedback of {circle around (1)} to {circle around (6)}, large current flows in the device so as to break the device.
Therefore, in design of the N channel type high sustaining voltage MOS transistor, conditions of the design is set considering the above-mentioned phenomenon. First, a transistor construction decreasing substrate current (ISub) is adopted because operation sustaining voltage (VSUS) becomes small as substrate current (ISub) becomes large, and second, the conditions are decided so as to decrease substrate current (ISub) at an actually used region.
FIG. 4
is a substrate current (ISub) vs. gate voltage (VG) characteristic view, in the figure, double humps characteristic of substrate current (ISub) at high region in gate voltage (VG) rises about the conventional N channel type high sustaining voltage MOS transistor (shown with a dotted line in the figure). Therefore, operation sustaining voltage (VSUS) is low shown in drain current (ID) vs. drain voltage (VD) characteristic view of
FIG. 5 and a
characteristic view showing operation sustaining voltage of FIG.
6
.
The double humps characteristic is caused by concentration of electric field by spreading the depletion layer near the N+ drain region at high region in gate voltage (VG).
Although it is considered to increase ion implantation volume (doze) and to rise concentration of N− type drain region as shown in
FIG. 6
to improve operation sustaining voltage (VSUS), the conventional semiconductor device is not improved enough in sustaining voltage as shown with white circles. Because concentration of end portion A of the N− type drain region
56
shown in
FIG. 12
rises conversely, problems of increase of short channel effect by that depletion layer spreads to the channel region
55
direction, increase of snap back phenomenon by increase of peak value of substrate current (ISub), and further decrease of voltage between source and drain (BVDS) occur. Therefore, there is not effective means improving operation-sustaining voltage.
Therefore, an object of the invention is to provide a semiconductor device capable of improving operation sustaining voltage and a method of manufacturing the device.
SUMMARY OF THE INVENTION
A semiconductor device of the invention has a gate electrode formed on at least one conductive type semiconductor substrate through a gate insulation film, a low concentration reverse conductive type drain region formed so as to be adjacent to the gate electrode, a high concentration reverse conductive type drain region separated from the other end of said gate electrode and included in said low concentration reverse conductive type drain region, and a middle concentration reverse conductive type layer having high impurity concentration peak at a position of the predetermined depth in said substrate at a region spanning at least from said gate electrode to said high concentration reverse conductive type drain region, and formed so that high impurity concentration becomes low at a region near surface of the substrate. Therefore, the semiconductor device is characterized in improving operation-sustaining voltage.
Especially said middle concentration reverse conductive type layer is formed at a region spanning at least from a position separated the predetermined space from said gate electrode to said high concentration reverse conductive type drain region. Therefore, electric field concentration at the end portion of the gate electrode can be defused and higher sustaining voltage becomes possible.
A method of manufacturing a semiconductor device has processes of forming a low concentration reverse conductive type drain region on at least one conductive type semiconductor substrate, forming a gate insulation film at the entire surface of said semiconductor substrate, forming a gate electrode overlapping at least upper side of said drain region by patterning after forming a conductive film on the entire surface, forming a high concentration reverse conductive type source region adjacent to one end of said gate electrode and a high concentration reverse conductive type drain region separated from the other end of said gate electrode and included in said low concentration reverse conductive type drain region, and forming a middle concentration reverse conductive type layer having high impurity concentration peak at a position of the predetermined depth in said substrate at a region spanning at least from the position having the predetermined space from said gate electrode to said high concentration reverse conductive type drain region, and formed so that high impurity concentration becomes lo
Kikuchi Shuichi
Nishibe Eiji
Suzuki Takuya
Elms Richard
Sanyo Electric Co,. Ltd.
Wilson Christian D.
LandOfFree
LDD high voltage MOS transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with LDD high voltage MOS transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and LDD high voltage MOS transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3317465