Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-05-28
2004-08-03
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S369000, C257S390000, C257S391000, C257S392000, C257S903000, C365S182000
Reexamination Certificate
active
06770940
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit of a CMOS structure including a plurality of static random access memories (SRAMs) and a plurality of logic circuits respectively accessing these SRAMs, and a method for fabricating the same.
A recent system LSI developed for portable equipment such as cellular phones includes a digital signal processor (DSP) required to perform high-speed processing of voice and moving image data and a central processing unit (CPU) responsible for processing of applications and system control during standby. A high-speed SRAM is necessary for the DSP as a buffer memory for transmit/receive data. Also, a SRAM is necessary for the DSP to be used as a work memory.
In conventional system LSIs for portable equipment, the threshold voltage (Vt) of MOS transistors tends to be set comparatively high for reduction of leakage current during standby. In such system LSIs, also, it is required to maintain the speed of the DSP and the CPU. Therefore, tight transistor design and circuit design are conventionally made in the tradeoff between the speed and the leakage current. In reality, processes specified for portable equipment, including increasing the threshold voltage slightly and increasing the gate length of MOS transistors slightly for avoiding a variation in leakage current, have been developed, separately from standard processes for non-portable equipment.
With the connection of portable equipment such as cellular phones to the Internet, the data processing amount of the portable equipment has sharply increased. In addition, the capacity of a memory for buffering data of moving images and data from the Internet has also increased.
In the situation described above, increase in leakage current due to the increased memory capacity has arisen concurrently with the request for high-speed operation of the DSP and the CPU. For solving these problems, the level of optimizing the transistor design and the circuit design as described above is no more useful.
The problem of reducing the leakage current may be solved by shutting off the power to circuits inside the LSI. However, since portable equipment, which is connected to a wireless network, has processing to be processed during standby, it is no more possible to simply shut off the power.
In the future, in mounting a number of circuit blocks having different uses on one chip, if fabrication processes optimized for the respective circuit blocks are individually adopted, the entire fabrication process will be complicated and thus the fabrication cost will increase.
SUMMARY OF THE INVENTION
An object of the present invention is providing a semiconductor integrated circuit in which a plurality of circuit blocks satisfying different performance requirements can be formed on one chip without complicating the fabrication process.
The present invention is applicable to a semiconductor integrated circuit of a CMOS structure including a first SRAM cell array required to operate at high speed and a second SRAM cell array operating at a speed lower than the speed of the first SRAM cell array. Power to the first SRAM cell array is shut off as required. For example, it is shut off during standby. Power to the second SRAM cell array is kept supplied even during the shutoff of power to the first SRAM cell array, for retention of data. Accordingly, the degree of necessity of leakage reduction during standby is low in the first SRAM cell array but high in the second SRAM cell array. In view of the above, according to the present invention, as for at least either N-channel MOS transistors or P-channel MOS transistors, MOS transistors of low Vt (threshold voltage of a transistor) are adopted for the first SRAM cell array for high-speed operation, and MOS transistors of high Vt are adopted for the second SRAM cell array for leakage reduction. For this adoption, first, the average channel width of MOS transistors constituting each of the first and second SRAM cell arrays is set at a half or less of the average channel width of MOS transistors constituting each of the other circuit blocks (for example, SRAM peripheral circuits and logic circuits), to thereby enable use of a “reverse narrow channel characteristic” (characteristic that the absolute value of Vt is smaller as the channel width is smaller) for the first and second SRAM cell arrays in which a high scale of integration is required. In addition, the channel impurity concentration of the MOS transistors of the second SRAM cell array is set higher than the channel impurity concentration of the MOS transistors of the first SRAM cell array by additional ion implantation. By this additional ion implantation, the decreased absolute value of Vt of the MOS transistors of the second SRAM cell array due to the reverse narrow channel effect is compensated, to provide MOS transistors of high Vt. The “high Vt” as used herein refers to that the absolute value of the threshold voltage of a MOS transistor, N-channel or P-channel, is large.
In place of the additional ion implantation, the thickness of a gate oxide film may be adjusted. More specifically, gate oxide films of the MOS transistors of the second SRAM cell array are set thicker than gate oxide films of the MOS transistors of the first cell array by film thickness adjustment. By this film thickness adjustment, also, the decreased absolute value of Vt of the MOS transistors of the second SRAM cell array due to the reverse narrow channel effect is compensated, to provide MOS transistors of high Vt.
A third SRAM cell array, which operates at a speed lower than that of the first SRAM cell array, as does the second SRAM cell array, and has a memory capacity larger than the second SRAM cell array, may be provided. In this case, even if the third SRAM cell array is formed under the high Vt transistor conditions as is the second SRAM cell array to reduce the leakage current per memory cell, the total leakage current flowing in all the memory cells of the third SRAM cell array during the operation of the third SRAM cell array will be too large to be negligible. According to the present invention, therefore, the third SRAM cell array, in which no data retention is required, is powered off as required.
As described above, according to the present invention, the reverse narrow channel characteristic of MOS transistors is used, the additional ion implantation for adjusting the channel impurity concentration or the adjustment of the thickness of the gate oxide film is adopted, and, low Vt or high Vt MOS transistors are selectively used for the respective circuit blocks depending on the operating speed and depending on whether or not power is shut off In this way, a plurality of circuit blocks satisfying different performance requirements can be mounted on one chip without complicating the fabrication process.
REFERENCES:
patent: 5285069 (1994-02-01), Kaibara et al.
patent: 6424015 (2002-07-01), Ishibashi et al.
patent: 2001/0038552 (2001-11-01), Ishimaru et al.
patent: 2003/0227060 (2003-12-01), Yamauchi
McDermott Will & Emery LLP
Prenty Mark V.
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