Synchronous semiconductor memory device

Details Synchronous semiconductor memory device Synchronous semiconductor memory device

1997-02-18

1998-01-13

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Signals

365222, 365233, G11C 800

Patent

active

057086117

ABSTRACT:
A refresh control circuit of a DLL circuit responds to an auto refresh detection signal AR and a self refresh detection signal SR to inhibit input of clock signals ECLK and RCLK to a phase comparator and to a voltage control delay circuit. The DLL circuit can be stopped in a mode where an internal clock signal is not required to reduce power consumption.

REFERENCES:
patent: 5444667 (1995-08-01), Obara
patent: 5469386 (1995-11-01), Obara
patent: 5477491 (1995-12-01), Shirai
patent: 5495452 (1996-02-01), Cha
patent: 5608682 (1997-03-01), Jinbo et al.
Natsuki Kushiymam et al., IEEE Journal of Solid-State Circuits, vol. 28, No. 4, "A 500 Megabyte/s Data-Rate 4.5M DRAM", Apr. 1993, pp.490-497.

Affiliated with

Also associated with

Rating

Synchronous semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-331627