Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-04-05
2004-11-23
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185230
Reexamination Certificate
active
06822900
ABSTRACT:
Japanese Patent Application No. 2001-115678, filed on Apr. 13, 2001, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device configured of a memory cell provided with two non-volatile memory elements that are controlled by one word gate and two control gates.
A known type of non-volatile semiconductor device is a metal-oxide-nitride-oxide semiconductor or substrate (MONOS), wherein a gate insulation layer between the channel and the gate is formed of a multi-layer stack of a silicon oxide film, a silicon nitride film, and a silicon oxide film, and charge is trapped in the silicon nitride film.
This MONOS type of non-volatile semiconductor memory device was disclosed by Y. Hayashi, et al, in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123. This document disclosed a twin MONOS flash memory cell provided with two non-volatile memory elements (MONOS memory cells) controlled by one word gate and two control gates. In other words, each flash memory cell has two charge-trapping sites.
A plurality of twin MONOS flash memory cells of this configuration are arranged in both a row direction and a column direction, to form a memory cell array region.
Two bit lines, one word line, and two control gate lines are required for driving this twin MONOS flash memory cell. It should be noted, however, that these lines can be connected in common if different control gates are set to the same potential during the driving of a large number of memory cells.
In this case, a flash memory operation is data erasure, programming, or reading. Data programming and reading is usually done for selected cells for eight or 16 bits simultaneously, but data erasure is simultaneously done over a much wider range.
In such a case, data disturbance becomes a cause of concern with this type of non-volatile memory. Data disturbance refers to the disturbance of data in non-selected cells, during programming or erasure done by repeating a programming state in which a high potential is applied even to cells within the non-selected sector region by the common wiring, during programming or erasure in which a high potential is applied to the control gate line and bit line of the selected cells.
To prevent such a situation, the configuration could be such that select gate circuit is provided to ensure that the high potential is applied only to cells in the selected sector, whereas so high potential is applied to cells in non-selected sector.
With such a configuration, however, the select gate circuit takes up some surface area, preventing a high degree of integration of the memory cells. In addition, if a voltage drop occurs in the select gates, it is necessary to supply an increased voltage to allow for that voltage drop, in order to supply a high potential to selected sectors during programming or erasure. As a result, low-voltage drive is impeded, making this unsuitable for equipment that demands a low power consumption, such as portable equipment in particular.
This provides plenty of room for improvements in high-speed drive, to cope with future requirements for faster reading of data in applications such as portable equipment.
BRIEF SUMMARY OF THE INVENTION
The present invention may provide a non-volatile semiconductor memory device that enables a high degree of integration without requiring selection gate circuit, while preventing any disturbance of data in cells in non-selected sectors during the programming or erasure of selected cells.
The present invention may also provide a non-volatile semiconductor device that prevents any voltage drop by making selection gate circuit unnecessary, thus reducing the power consumption thereof.
The present invention may further provide a non-volatile semiconductor device enabling high-speed drive by reducing load capacity of control gate lines to which high potentials are supplied.
According to one aspect of the present invention, there is provided a non-volatile semiconductor memory device has a memory cell array region in which are disposed a plurality of memory cells in both a column direction and a row direction, each of the memory cells having first and second non-volatile memory elements that are controlled by one word gate and first and second control gates. The non-volatile semiconductor memory device further provided with a control gate drive section which drives the first and second control gates of the memory cells within the memory cell array region.
The memory cell array region is divided in the row direction into a plurality of sector regions. Each of the sector regions has a plurality of memory cells disposed in each of columns arrayed in the column direction.
Each of the sector regions is divided into a plurality of blocks in the column direction. The control gate drive section has a plurality of control gate drivers for each of the sector regions. Each of the control gate drivers is disposed to correspond to at least one block of the plurality of blocks, to set the potentials of the first and second control gates of all the memory cells within the corresponding block.
During programming of a selected cell disposed in a block within a certain sector region, a control gate potential of a memory cell (selected cell and non-selected cell) in that block can be set to a programming potential by the corresponding control gate driver. Since other blocks in that sector region or and non-selected sector regions can be set to have a potential other than the programming potential by the corresponding control gate drivers, there is no disturbance of data within non-selected cells in the non-selected sector regions. Since this can also be achieved without the use of a select gate circuit, it enables a high degree of integration of the memory cells. In addition, since there is no voltage drop over the select gate circuit, low-voltage drive is enabled, making this memory particularly advantageous for portable equipment. Furthermore, since only memory cells within at least one block are connected to each control gate driver, the load capacity (gate capacity) connected to the control gate lines can be reduced in comparison with a configuration in which all the memory cells within one sector region are connected thereto. This enables high-speed drive of the memory.
Each of the blocks may be divided in the column direction into a plurality of large blocks and each of the large blocks may be further divided in the column direction into a plurality of small blocks.
In this case, each of the control gate drivers may be disposed to correspond to one of the large blocks, to set the potentials of the first and second control gates of all the memory cells disposed within the small blocks provided in the corresponding large block.
Alternatively, each of the control gate drivers may be disposed to correspond to one of the small blocks provided in each of the large blocks, to set the potentials of the first and second control gates of all the memory cells disposed within the corresponding small block.
When data is erased, one of the control gate drivers may be selected and supply a high potential for erasure to all of the first and second control gates within the corresponding sector region, to erase data in a batch in each of the plurality of sector regions.
A plurality of control gate lines may be formed to extend in the column direction in each of the sector regions, and the control gate drive section may be connected directly to the control gate lines disposed in each of the sector regions, with no intervening gate circuit.
This ensures that no high potential is applied to non-selected cells within non-selected sector regions, even when the gate circuit that would increase the surface area and generate a voltage drop has been removed.
In this case, the control gate lines may include: a plurality of main control gate lines connected directly to the control gate drive section; and a plurality of sub-control gate lines that connect the main control gate lines to the f
Nguyen Tan T.
Oliff & Berridg,e PLC
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