Non-volatile semiconductor memory device having a memory...

Details Non-volatile semiconductor memory device having a memory... Non-volatile semiconductor memory device having a memory...

2002-12-31

2004-11-02

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185230, C365S185280

Reexamination Certificate

active

06813188

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and specifically, to a non-volatile semiconductor memory device with memory cells having a layered film of an oxide film, an nitride film, and another oxide film (hereinafter referred to as an “ONO film”).
2. Description of the Background Art
As one type of an MONOS (Metal OxyNitride Oxide Semiconductor) non-volatile semiconductor memory device which itself is one implementation of a non-volatile semiconductor memory device, an NROM (Nitrided Read Only Memory)
120
as shown in
FIG. 13
may be found which can handle 2 bits of information per one memory cell
110
.
In each of the memory cells, for example as shown in
FIG. 14
, an ONO film
105
, formed with silicon oxide films
105
a
and
105
c
, and a silicon nitride film
105
b
, is formed on a semiconductor substrate
101
. The ONO film
105
has a floating gate structure, and silicon nitride film
105
b
among the three layered films forming ONO film
105
serves as the floating gate.
In one region and the other region of semiconductor substrate
101
respectively positioned at opposing sides of ONO film
105
, a pair of impurity regions
103
a
and
103
b
are formed as source/drain regions. On ONO film
105
, a control gate electrode
107
of polysilicon film or polycide structure, for example, is formed.
Information is written by injecting channel hot electrons (hereinafter simply referred to as “electrons”) into two portions in silicon nitride film
105
b
separately, which are respectively positioned at the side near one impurity region
103
a
and at the side near the other impurity region
103
b
, of the pair of impurity regions
103
a
and
103
b
. Thus, 2 bits of information can be handled per one cell.
Next, an information write operation of the non-volatile semiconductor memory device will be described. First, as shown in
FIG. 14
, no information is written in the memory cell in the initial state, and a voltage of 0V is applied to control gate electrode
107
of the memory cell, a pair of impurity regions
103
a
and
103
b
, and semiconductor substrate
101
, respectively.
Next, as shown in
FIG. 13
, a word line WL
1
is selected by a row decoder
115
and control gate electrode
107
of memory cell
110
is connected to a word line voltage generating circuit
111
. Bit lines BL
2
and BL
3
are selected by a column decoder
117
.
Thus, as shown in
FIG. 15
, a prescribed voltage of 9V is applied to control gate electrode
107
. A voltage of 0V is applied to impurity region
103
a
, and a voltage of 5V is applied to impurity region
103
b
.
At this time, electrons flow from impurity region
103
a
toward impurity region
103
b
, and electrons
121
which turned to be the channel hot electrons near impurity region
103
b
are injected into silicon nitride film
105
b
of ONO film
105
.
Thereafter, as shown in
FIG. 16
, a voltage of 0V is applied to control gate electrode
107
, a pair of impurity regions
103
a
and
103
b
, and semiconductor substrate
101
, respectively.
In the state shown in
FIG. 16
, electrons
121
injected into the portion near impurity region
103
b
in silicon nitride film
105
b
will not shift from its location toward impurity region
103
a
. Thus, 1 bit of information is written into one memory cell
110
.
Next, an operation for writing further 1 bit of information into that one memory cell
110
will be described. First, from the state shown in
FIG. 17
in which 1 bit of information is written (the same state shown in FIG.
16
), bit lines BL
2
and BL
3
of memory cell
110
are selected by column decoder
117
as described above. Then, by a row decoder
115
, control gate electrode
107
is connected to word line voltage generating circuit
111
.
Thus, as shown in
FIG. 18
, the prescribed voltage of 9V is applied to control gate electrode
107
. A voltage of 5V is applied to impurity region
103
a
, and a voltage of 0V is applied to impurity region
103
b.
At this time, electrons flow from impurity region
103
b
toward impurity region
103
a
, and electrons
121
which turned to be the channel hot electrons near impurity region
103
a
are injected into silicon nitride film
105
b
of ONO film
105
. Thereafter, as shown in
FIG. 19
, a voltage of 0V is applied to control gate electrode
107
, a pair of impurity regions
103
a
and
103
b
, and semiconductor substrate
101
, respectively.
In the state shown in
FIG. 19
, electrons
121
injected into the portion near impurity region
103
a
in silicon nitride film
105
b
will not shift from its location toward impurity region
103
b
. Thus, 2 bits of information is written into one memory cell
110
of the non-volatile semiconductor memory device.
In the conventional semiconductor memory device described above, however, following problems exist. Generally, each process of manufacturing semiconductor devices involves manufacturing variations. When forming ONO film
105
of the non-volatile semiconductor memory device described above, silicon oxide films
105
a
and
105
c
vertically sandwiching silicon nitride film
105
b
are normally formed such that both of the films have the same thickness.
On the other hand, when films vary in thickness at steps of forming the silicon oxide films, silicon oxide film
105
a
of the lower layer may be formed thinner than silicon oxide film
105
c
of the upper layer, for example as shown in FIG.
20
. On the contrary, silicon oxide film
105
c
of the upper layer may be formed thinner than silicon oxide film
105
a
of the lower layer.
As shown in
FIG. 22
, when a write operation is performed to a non-volatile semiconductor memory device having ONO film
105
in which lower silicon oxide film
105
a
is formed thinner than upper silicon oxide film
105
c
, electrons
121
turned to be the channel hot electrons near impurity region
103
b
are injected into silicon nitride film
105
b
in a portion near upper silicon oxide film
105
c
, or injected into a portion of silicon oxide film
105
c.
Thus, as shown in
FIG. 23
, electrons
121
are stored (trapped) in that portion.
As shown in
FIG. 24
, when a write operation is performed to a non-volatile semiconductor memory device having ONO film
105
in which upper silicon oxide film
105
c
is formed thinner than lower silicon oxide film
105
a
, electrons
121
turned to be the channel hot electrons near impurity region
103
b
are injected into silicon nitride film
105
b
in a portion near lower silicon oxide film
105
a
, or injected into a portion of silicon oxide film
105
a.
Thus, as shown in
FIG. 25
, electrons
121
are stored (trapped) in that portion.
In such states, electrons
121
can not be retained stably in silicon nitride film
105
b
, and electrons
121
may leak from the portions near silicon oxide films
105
a
and
105
c
, for example after a long time period. Further, electrons
121
injected into one side of silicon nitride film
105
b
may shift toward the other side.
As a result, the memory characteristics are degraded and the reliability of the non-volatile semiconductor device is impaired.
SUMMARY OF THE INVENTION
The present invention is contemplated to solve the above mentioned problems, and the object thereof is to provide a non-volatile semiconductor memory device that retains charges as information stably.
The semiconductor memory device according to the present invention includes memory cells and voltage applying circuit. A memory cell includes a pair of impurity regions formed spaced apart from each other on a main surface of a semiconductor substrate, a first insulating film formed on a region between the pair of impurity regions on the semiconductor substrate, a second insulating film formed on the first insulating film for storing charges as information, a third insulating film formed on the second insulating film, and an electrode portion formed on the third insulating film for controlling shift of charges relative to the second insulating film. The voltage applyin

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