Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
2002-02-01
2004-02-03
Pert, Evan (Department: 2811)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S051000, C438S106000, C438S117000
Reexamination Certificate
active
06686227
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed in general to integrated circuits and, more specifically, to a method and system for exposed die molding for integrated circuit packaging.
BACKGROUND OF THE INVENTION
A conventional plastic integrated circuit package generally comprises a lead frame or substrate, an integrated circuit die made of silicon, and a protective layer to protect the die and the electrical connections between the die and the substrate.
The protective layer is generally formed in the integrated circuit package through the use of a mold. The integrated circuit is placed between an upper mold and a lower mold while the material of the protective layer is injected around the integrated circuit, after which the material is allowed to harden. Recent improvements in this process have included the use of a flexible material between the upper mold and the integrated circuit in order to prevent damage to the integrated circuit from the hard surface of the upper mold.
The integrated circuit is typically applied to the substrate with an adhesive layer. Based on possible characteristics of the adhesive layer, the molding process has to accommodate a specified variation associated with the integrated circuit package. These characteristics generally include bondline thickness and tilt.
Bondline thickness is the average thickness of the adhesive layer in an integrated circuit. The molding process has to accommodate the variation in bondline thickness, or the bondline thickness consistency, for all the integrated circuits in a set of integrated circuits being processed. Thus, for example, if the minimum average thickness of the adhesive layer is 20 microns and the maximum average thickness of the adhesive layer is 50 microns, the bondline thickness consistency is 30 microns. In this situation, the molding process has to accommodate 30 microns for bondline thickness.
Tilt is the difference between the minimum and maximum thickness of an adhesive layer in an integrated circuit. The molding process has to accommodate the tilt variation for all the integrated circuits in a set of integrated circuits being processed. Thus, for example, if the minimum tilt of the adhesive layer is 0 microns and the maximum tilt of the adhesive layer is 30 microns, the tilt variation is 30 microns. In this situation, the molding process has to accommodate 30 microns for tilt variation.
Thus, using the above examples, the molding process has to accommodate an overall variation of 60 microns while processing a particular set of integrated circuits. This variation has to be accommodated in order to avoid die damage and to prevent flash from flowing onto the die.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and system for exposed die molding for integrated circuit packaging are provided. In particular, a floating plunger is provided as part of a lower mold during the molding process in order to accommodate greater variation in bondline thicknesses.
According to one embodiment of the present invention, a method for exposed die molding for integrated circuit packaging is provided that includes providing a mold comprising an upper mold with a flexible material, a lower mold, and a floating plunger. A substrate of an integrated circuit structure is clamped between the upper mold and the lower mold. An integrated circuit die of the integrated circuit structure is clamped between the floating plunger and the upper mold through the flexible material.
According to another embodiment of the present invention, a method for exposed die molding for integrated circuit packaging is provided that includes providing a mold comprising an upper mold, a lower mold, and a floating plunger. An integrated circuit die with a flexible material is provided. The integrated circuit die is coupled to a substrate. The substrate is clamped between the upper mold and the lower mold. The integrated circuit die is clamped between the floating plunger and the upper mold through the flexible material.
According to yet another embodiment of the present invention, a system for exposed die molding for integrated circuit packaging is provided that includes an integrated circuit structure, a mold, and a flexible material. The integrated circuit structure comprises an integrated circuit die and a substrate. The mold comprises an upper mold, a lower mold, and a floating plunger. The upper mold and the lower mold are operable to clamp the substrate. The floating plunger and the upper mold, through the flexible material, are operable to clamp the integrated circuit die.
Technical advantages of one or more embodiments of the present invention include providing an improved method for exposed die molding for integrated circuit packaging. In a particular embodiment, a floating plunger is provided as part of a lower mold during the molding process for a set of integrated circuits. As a result, the variation in bondline thicknesses that may be accommodated is greatly increased.
In another embodiment, the floating plunger is operable to be tilted at an angle in accordance with the angle associated with the tilt of the adhesive layer. As a result, the variation in tilt that may be accommodated is greatly increased.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.
REFERENCES:
patent: 5049526 (1991-09-01), McShane et al.
patent: 5656549 (1997-08-01), Woosley et al.
Hundt Michael J.
Zhou Tiao
Jorgenson Lisa K.
Munck William A.
Pert Evan
Sarkar Asok Kumar
STMicroelectronics Inc.
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